Patent Assignment
Reel/Frame 068519/0711
Assignment of Assignor's Interest
Recorded: 2024-09-07
Pages: 3
Assignors
GUO, JIACEN
Executed: 2024-03-21
CAO, WEI
Executed: 2024-04-30
YANG, XIANG
Executed: 2024-03-21
Assignee
WESTERN DIGITAL TECHNOLOGIES, INC.
5601 GREAT OAKS PARKWAY, SAN JOSE, CALIFORNIA, 95119
Covered Property
(1)
Single-Level Memory Cell Error on-Chip Detection
Application:
18/442,693 →
Publication:
US 2025/0266110
Related Assignments
(5)
Other recorded transfers of the patent in this record — the chain of ownership.
Patent Collateral Agreement (Ar)
May 15, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 067417/0329 →
Assignment of Assignor's Interest
Oct 11, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069169/0572 →
Security Agreement (Supplemental)
Nov 14, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0486 →
Security Agreement
Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
Partial Release of Security Interests
Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →