IP Library Granted Patent US 10,361,281
Granted Patent B2
US 10,361,281 · App. 15/911,892 · Granted Jul 23, 2019

Method to improve reliability of replacement gate device

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Quick Facts
Patent No.
US 10,361,281
App. No.
15/911,892
Filed
Mar 5, 2018
Granted
Jul 23, 2019
Kind
B2
Art Unit
2816
USPC
438/595
Abstract

A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

Claims (35)

1. A method of fabricating a gate stack for a semiconductor device, said method comprising steps of:

after removal of a dummy gate, providing a replacement gate structure by performing steps of:

forming a dielectric layer over an area vacated by the dummy gate;

depositing a metal layer over the dielectric layer, the metal layer comprising a thermally stable metal alloy selected from the group consisting of TiN, TaC, TaN, TaC and combinations thereof;

depositing a sacrificial layer over the metal layer;

performing a first thermal anneal;

removing the sacrificial layer from the metal layer to expose a portion of the thin metal layer directly over a channel region of the semiconductor device;

depositing a work function metal on the metal layer comprising the thermally stable metal alloy; and

depositing a metal layer of low resistivity metal on the work function metal layer in the gate stack.

2. The method of claim 1 , further comprising:

performing a second rapid thermal anneal after annealing the structure.

3. The method of claim 2 , performing the second rapid thermal anneal comprises performing a millisecond anneal with a laser.

4. The method of claim 2 , wherein performing the second rapid thermal anneal comprises performing a millisecond anneal with a flash lamp.

5. The method of claim 1 , wherein performing the first rapid thermal anneal comprises annealing at a temperature between 800° C. and 1100° C.

6. The method of claim 5 , wherein performing the first rapid thermal anneal further comprises spiking the temperature for a period of time up to five seconds.

7. The method of claim 6 , wherein performing the first rapid thermal anneal comprises annealing the structure in ambient nitrogen.

8. The method of claim 1 , wherein depositing the sacrificial layer comprises depositing a layer of polycrystalline silicon.

9. The method of claim 1 , wherein depositing the sacrificial layer comprises depositing a layer of amorphous silicon.

10. A method of fabricating a gate stack for a semiconductor device, said method comprising steps of:

after removal of a dummy gate, providing a replacement gate structure by performing steps of:

growing a dielectric layer over an area vacated by the dummy gate;

depositing a thermally metal layer over the dielectric layer;

depositing a sacrificial layer over the thermally stable metal layer;

performing a first anneal;

depositing a work function metal on the thermally stable metal layer, the work function metal having a composition selected from the group consisting of TiN, TiAl and combinations thereof;

depositing a metal layer of low resistivity metal directly on the work function metal layer in the gate stack; and

performing a second anneal.

11. The method of claim 10 , performing the second anneal comprises performing a millisecond anneal with a laser.

12. The method of claim 11 , wherein performing the second anneal comprises performing a millisecond anneal with a flash lamp.

13. The method of claim 10 , wherein performing the first anneal comprises annealing at a temperature between 800° C. and 1100° C.

14. The method of claim 13 , wherein performing the first anneal further comprises spiking the temperature for a period of time up to five seconds.

15. The method of claim 14 , wherein performing the first anneal comprises annealing the structure in ambient nitrogen.

16. The method of claim 10 , wherein depositing the sacrificial layer comprises depositing a layer of polycrystalline silicon.

17. The method of claim 10 , wherein depositing the sacrificial layer comprises depositing a layer of amorphous silicon.

18. The method of claim 10 , wherein removing the dummy gate comprises a selective etch.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2018
From: ANDO, TAKASHI; CARTIER, EDUARD A.; CHOI, KISIK; NARAYANAN, VIJAY
To: INTERNATIONAL BUSINESS MACHINES CORPORATION; GLOBALFOUNDRIES INC.
Reel/Frame 045108/0029 →