IP Library Granted Patent US 7,804,167
Granted Patent B2
US 7,804,167 · App. 11/565,701 · Granted Sep 28, 2010

Wire bond integrated circuit package for high speed I/O

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Quick Facts
Patent No.
US 7,804,167
App. No.
11/565,701
Filed
Dec 1, 2006
Granted
Sep 28, 2010
Kind
B2
Examiner
CHEN, YU
Art Unit
2815
USPC
257/691
Abstract

An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.

Claims (37)

1. An integrated circuit package comprising:

a package substrate;

a die attach pad formed on the package substrate for securing a die to the package substrate;

a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate;

a first plurality of bond fingers formed immediately adjacent to an inside of the ground bonding ring for attaching a set of transmit I/O signal bond wires between the package substrate and the die;

a power bonding ring formed immediately adjacent to an outside of the ground bonding ring for attaching I/O and core power bond wires between the die and the package substrate, wherein the ground bonding ring is disposed between the power bonding ring and the first plurality of bond fingers;

a second plurality of bond fingers formed immediately adjacent to an outside of the power bonding ring for attaching a set of receive I/O signal bond wires between the package substrate and the die, wherein the power bonding ring is disposed between the second plurality of bond fingers and the ground bonding ring; and

a third plurality of bond fingers formed immediately outside the second plurality of bond fingers for attaching another set of I/O signal bond wires between the package substrate and the die, wherein the second plurality of bond fingers is disposed between the third plurality of bond fingers and the power bonding ring;

wherein the power bonding ring is electrically connectable to a first voltage source;

wherein the ground bonding ring is electrically connectable to a second voltage source which is separate from the first voltage source;

wherein the set of transmit I/O signal bond wires are of shorter length than the set of receive I/O signal bond wires.

2. The integrated circuit package of claim 1 wherein the transmit I/O signal bond wires are one millimeter or less in length.

3. The integrated circuit package of claim 1 further comprising the ground bonding ring formed in the die attach pad.

4. The integrated circuit package of claim 1 wherein the I/O and core power bond wires are routed in between the transmit I/O signal bond wires.

5. The integrated circuit package of claim 1 wherein the power bonding ring comprises a plurality of physically divided segments for connecting the I/O and core power, bond wires to multiple voltage sources.

6. The integrated circuit package of claim 1 , the integrated circuit package substrate excluding plating tails.

7. The integrated circuit package of claim 1 , the integrated circuit package substrate further comprising a plurality of vias for electrically connecting the first plurality of bond fingers to at least one lower layer of the package substrate.

8. The integrated circuit package of claim 7 , the integrated circuit package substrate further comprising a plurality of ball pads formed on the package substrate directly below the first plurality of bond fingers for connecting the package substrate to a printed circuit board, each of the ball pads electrically connected to one of the plurality of vias.

9. The integrated circuit package of claim 1 , wherein at least one of the power bonding ring and the ground bonding ring is a single continuous ring.

10. The integrated circuit package of claim 1 , wherein the integrated circuit package substrate comprises one or more plating tails.

11. A method of making an integrated circuit package comprising steps of:

providing a package substrate;

forming a die attach pad on the package substrate for securing an integrated circuit die to the package substrate;

forming a ground bonding ring on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate; and

forming a first plurality of bond fingers immediately adjacent to an inside of the ground bonding ring for attaching a set of transmit I/O signal bond wires between the package substrate and the die;

forming a power bonding ring immediately adjacent to an outside of the mind bonding ring for attaching core and I/O power bond wires between the die and the package substrate, wherein the ground bonding ring is disposed between the power bonding ring and the first plurality of bond fingers;

forming a second plurality of bond fingers immediately adjacent to an outside of the power bonding it for attaching a set of receive I/O signal bond wires between the package substrate and the die, wherein the power bonding ring is disposed between the second plurality of bond fingers and the ground bonding ring; and

forming a third plurality of, bond fingers immediately outside the second plurality of bond fingers for attaching another set of I/O signal bond wires between the package substrate and the die, wherein the second plurality of bond fingers is disposed between the third plurality of bond fingers and the power bonding ring;

wherein the power bonding ring is electrically connectable to a first voltage source;

wherein the ground bonding ring is electrically connectable to a second voltage source which is separate from the first voltage source;

wherein the set of transmit I/O signal bond wires are of shorter length than the set of receive I/O signal bond wires.

12. The method of claim 11 further comprising forming the ground bonding ring in the die attach pad.

13. The method of claim 11 wherein the core and I/O power bond wires are routed in between the transmit I/O signal bond wires.

14. The method of claim 11 further comprising a step of forming the power bonding ring in segments for connecting the I/O and core power bond wires to multiple voltage sources.

15. The method of claim 11 further comprising steps of forming plating tails in the package substrate for an electroplating process and removing the plating tails after the electroplating process.

16. The method of claim 11 further comprising forming a plurality of vias for electrically connecting the first plurality of bond fingers to at least one lower layer of the package substrate.

17. The method of claim 11 further comprising forming a plurality of ball pads on the package substrate directly below one of the first plurality of bond fingers for connecting the package substrate to a printed circuit board, each of the ball pads electrically connected to one of the plurality of vias.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →