Memory system with Fin FET technology
View Patent ↗A method for manufacturing a memory system is provided including forming a charge-storage layer on a first insulator layer including insulating the charge-storage layer from a vertical fin, forming a second insulator layer from the charge-storage layer, and forming a gate over the second insulator includes forming a fin field effect transistor.
1. A method for manufacturing a memory system comprising:
forming a vertical fin of a semiconductor substrate being a continuous layer, the vertical fin protruding vertically, and being part of the semiconductor substrate;
forming a charge-storage layer on a first insulator layer including insulating the charge-storage layer from the vertical fin;
forming a second insulator layer from the charge-storage layer;
removing at least portions of the first insulator layer, the charge storage layer and the second insulator layer from above the vertical fin such that the charge storage layer is isolated on both sides of the vertical fin; and
forming a gate over the vertical fin to thereby form a fin field effect transistor.
2. The method as claimed in claim 1 wherein forming the charge-storage layer includes forming a silicon rich nitride layer.
3. The method as claimed in claim 1 wherein the fin field effect transistor is a self aligned SONOS fin field effect transistor.
4. The method as claimed in claim 1 wherein forming the second insulator layer includes steam oxidizing an outer portion of the charge-storage layer.
5. The method as claimed in claim 1 further comprising:
forming a memory sub-system with the memory system; and
forming a device, a printed circuit board, or an electronic system with the memory sub-system.
6. A method for manufacturing a memory system comprising:
forming a vertical fin of a semiconductor substrate being a continuous layer, the vertical fin protruding vertically, and being part of the semiconductor substrate and having a sloped sidewall substantially vertical, wherein the vertical fin is capped by an oxide layer, and the oxide layer is in direct contact with a word line;
forming a silicon rich nitride layer on a first dielectric layer including insulating the silicon rich nitride layer from the vertical fin, wherein the silicon rich nitride layer is a charge-storage layer;
steam oxidizing a second dielectric layer from the charge-storage layer; and
forming the word line over the vertical fin to thereby form a fin field effect transistor.
7. The method as claimed in claim 6 wherein steam oxidizing the second dielectric layer on the charge-storage layer includes isolating the silicon rich layer from the word line.
8. The method as claimed in claim 6 wherein the fin field effect transistor is a self aligned SONOS fin field effect transistor.
9. The method as claimed in claim 6 wherein forming the silicon rich nitride layer includes forming a gradient concentration of silicon in the silicon rich nitride layer.
10. The method as claimed in claim 6 further comprising patterning the word line on the second dielectric layer.
11. A memory system comprising:
a semiconductor substrate being a continuous layer;
a vertical fin formed of the semiconductor substrate, the vertical fin protruding vertically, and being part of the semiconductor substrate;
a plurality of first insulator layers on both sides of the vertical fin;
a plurality of charge-storage layers on each of the first insulator layers, wherein the charge-storage layers are isolated on both sides of the vertical fin;
a plurality of second insulator layers on the charge-storage layers; and
a gate on the vertical fin.
12. The system as claimed in claim 11 wherein the charge-storage layer includes a silicon rich nitride layer.
13. The system as claimed in claim 11 further comprising a self aligned SONOS fin field effect transistor formed on the vertical fin.
14. The system as claimed in claim 11 wherein the second insulator layer includes the charge-storage layer having an outer portion oxidized.
15. The system as claimed in claim 11 further comprising:
a memory sub-system with the memory system; and
a device, a printed circuit board, or an electronic system with the memory sub-system.
16. The system as claimed in claim 11 wherein:
the first insulator layers are first dielectric layers on the vertical fin;
the charge-storage layers are silicon rich nitride layers on the first insulator layers;
the second insulator layers are second dielectric layers from the charge-storage layers; and
the gate is a poly-silicon gate on the second dielectric layers.
17. The system as claimed in claim 16 wherein the second dielectric layer on the charge-storage layer isolates the charge-storage layer from a word line.
18. The system as claimed in claim 16 further comprising a self aligned SONOS fin field effect transistor.
19. The system as claimed in claim 16 wherein the charge-storage layer includes the silicon rich nitride layer having a gradient concentration.
20. The system as claimed in claim 16 further comprising a word line patterned on the second dielectric layer.
21. The method of claim 1 , further comprising:
forming the first insulator layer continuously on sidewalls and over the vertical fin.