Method and apparatus for a 1 of N signal
The present invention comprises a method and apparatus for an integrated circuit (IC) that uses 1 of N signals to reduce the circuit's wire to wire effective capacitance. The present invention comprises a logic tree circuit coupled to a first 1 of N input signal, a second 1 of N input signal, and a 1 of N output signal where the 1 of N signals' reduce the signal's wire to wire effective capacitance. Other embodiments of the present invention include the use of a 1 of 2 signal, a 1 of 3 signal, a 1 of 4 signal, and a 1 of 8 signal where one and one of the wires of the signal is active.
1. A 1 of N signal used to convey multiple values of information between N-NARY logic circuits in an integrated circuit, comprising:
a bundle of N wires routed together between different N-NARY logic circuits in the integrated circuit wherein at most one wire of said bundle of N wires is active during an evaluation cycle and where N is greater than 2; and
a 1 of N encoding that encodes said bundle of N wires to indicate multiple values of information conveyed by said bundle of N wires wherein at most one wire of said bundle of N wires is true during said evaluation cycle.
2. The 1 of N signal of claim 1 wherein said bundle of N wires comprises a number of wires from the following group: a bundle of 3 wires, a bundle of 4 wires, or a bundle of 8 wires.
3. The 1 of N signal of claim 1 wherein said 1 of N encoding comprises a not valid value wherein zero wires of said bundle of N wires is active.
4. The 1 of N signal of claim 1 wherein said 1 of N encoding on said bundle of N wires cooperatively operate to reduce the power consumption in the integrated circuit according to the number of wires in said bundle of N wires evaluating per bit of encoded information.
5. A system that uses a 1 of N signal to convey multiple values of information between N-NARY logic circuits in an integrated circuit, comprising:
a bundle of N wires routed together between different N-NARY logic circuits in the integrated circuit wherein at most one wire of said bundle of N wires is active during an evaluation cycle and where N is greater than 2; and
a 1 of N encoding that encodes said bundle of N wires to indicate multiple values of information conveyed by said bundle of N wires wherein at most one wire of said bundle of N wires is true during said evaluation cycle.
6. The system of claim 5 wherein said bundle of N wires comprises a number of wires from the following group: a bundle of 3 wires, a bundle of 4 wires, or a bundle of 8 wires.
7. The system of claim 5 wherein said 1 of N encoding comprises a not valid value wherein zero wires of said bundle of N wires is active.
8. The system of claim 5 wherein said 1 of N encoding on said bundle of N wires cooperatively operate to reduce the power consumption in the integrated circuit according to the number of wires in said bundle of N wires evaluating per bit of encoded information.
9. A method that uses a 1 of N signal to convey multiple values of information between N-NARY logic circuits in an integrated circuit, comprising:
encoding multiple values of information with a 1 of N encoding where N is greater than 2; and
conveying said 1 of N encoded information through a bundle of N wires routed together between different N-NARY logic circuits in the integrated circuit wherein at most one wire of said bundle of N wires is active and true during an evaluation cycle.
10. The method of claim 9 wherein said bundle of N wires comprises a number of wires from the following group: a bundle of 3 wires, a bundle of 4 wires, or a bundle of 8 wires.
11. The method of claim 9 wherein said 1 of N encoding comprises a not valid value wherein zero wires of said bundle of N wires is active.
12. The method of claim 9 wherein said 1 of N encoding on said bundle of N wires cooperatively operate to reduce the power consumption in the integrated circuit according to the number of wires in said bundle of N wires evaluating per bit of encoded information.
13. A method that provides an integrated circuit with a 1 of N signal to convey multiple values of information between N-NARY logic circuits, comprising:
providing a bundle of N wires routed together between different N-NARY logic circuits in the integrated circuit wherein at most one wire of said bundle of N wires is active during an evaluation cycle and where N is greater than 2; and
providing a 1 of N encoding that encodes said bundle of N wires to indicate multiple values of information conveyed by said bundle of N wires wherein at most one wire of said bundle of N wires is true during said evaluation cycle.
14. The method of claim 13 wherein said bundle of N wires comprises a number of wires from the following group: a bundle of 3 wires, a bundle of 4 wires, or a bundle of 8 wires.
15. The method of claim 13 wherein said 1 of N encoding comprises a not valid value wherein zero wires of said bundle of N wires is active.
16. The method of claim 13 wherein said 1 of N encoding on said bundle of N wires cooperatively operate to reduce the power consumption in the integrated circuit according to the number of wires in said bundle of N wires evaluating per bit of encoded information.