IP Library › Assignment 018923/0404
Patent Assignment
Reel/Frame 018923/0404

Security Agreement

Recorded: 2007-02-12 Pages: 18
Assignor
INTRINSITY, INC.
Executed: 2007-01-01
Assignee
SILICON VALLEY BANK
3003 TASMAN DRIVE, SANTA CLARA, CALIFORNIA, 95054
Covered Properties (79)
Method and Apparatus for a N-Nary Logic Circuit Using 1 of N Signals
Patent: 6,069,497 →
Application: 09/019,244 →
Method and Apparatus for a 1 of N Signal
Patent: 6,911,846 →
Application: 09/019,278 →
Method and Apparatus for an N-Nary Logic Circuit Using 1 of 4 Signals
Patent: 6,066,965 →
Application: 09/019,355 →
Method and Apparatus for Routing 1 of N Signals
Patent: 6,202,194 →
Application: 09/073,478 →
Method and Apparatus for Routing 1 of 4 Signals
Patent: 6,211,456 →
Application: 09/073,479 →
A Method and Apparatus for Selecting an Intermediate Result for Parallel Normalization and Rounding Technique for Floating Point Arithmetic Operations
Patent: 6,173,299 →
Application: 09/120,771 →
Method and Apparatus for Parallel Normalization and Rounding Technique for Floating Point Arithmetic Operations
Patent: 6,185,593 →
Application: 09/120,775 →
Method and Apparatus for Formatting an Intermediate Result for Parallel Normalization and Rounding Technique for Floating Point Arithmetic Operations
Patent: 6,151,615 →
Application: 09/120,776 →
Shifting for Parallel Normalization and Rounding Technique for Floating Point Arithmetic Operations
Patent: 6,175,847 →
Application: 09/120,814 →
Method and Apparatus for TW0-Stage Address Generation
Patent: 6,209,076 →
Application: 09/122,504 →
Method and Apparatus for Logic Circuit Transition Detection
Patent: 6,404,233 →
Application: 09/123,742 →
Method and Apparatus for Logic Circuit Speed Detection
Patent: 6,088,830 →
Application: 09/124,207 →
Method and Apparatus for a Ram Circuit Having N-Nary Word Line Generation
Patent: 6,069,836 →
Application: 09/150,162 →
Method and Apparatus for a Ram Circuit Having N-Nary Output Interface
Patent: 6,046,931 →
Application: 09/150,258 →
Method and Apparatus for an Address Triggered Ram Circuit
Patent: 6,118,716 →
Application: 09/150,389 →
Method and Apparatus for an N-Nary Hpg Gate
Patent: 6,223,199 →
Application: 09/150,575 →
Method and Apparatus for an N-Nary Sum/Hpg Adder/Subtractor Gate
Patent: 6,219,686 →
Application: 09/150,717 →
Method and Apparatus for an N-Nary Sum/Hpg Gate
Patent: 6,219,687 →
Application: 09/150,720 →
Method and Apparatus for an N-Nary Adder Gate
Patent: 6,216,146 →
Application: 09/150,829 →
Method and Apparatus for Logic Synchronization
Patent: 6,118,304 →
Application: 09/179,330 →
Method and Apparatus That Allows the Logic State of a Logic Gate to Be Tested When Stopping or Starting the Logic Gate's Clock
Patent: 6,233,707 →
Application: 09/179,626 →
Method and Apparatus for Generating Clock Signals
Patent: 6,288,589 →
Application: 09/179,745 →
Method and Apparatus for an Enhanced Floating Point Unit with Graphics and Integer Capabilities
Patent: 6,275,838 →
Application: 09/181,405 →
Method and Apparatus for a Late Pipeline Enhanced Floating Point Unit
Patent: 6,460,134 →
Application: 09/181,406 →
1 of 4 Multiplier
Patent: 6,275,841 →
Application: 09/186,843 →
Method and Apparatus for Built-in Self-Test of Logic Circuitry
Patent: 6,272,653 →
Application: 09/191,813 →
Method and Apparatus for Saturation in an N-Nary Adder/Subtractor
Patent: 6,301,597 →
Application: 09/195,024 →
Method and Apparatus for Interruption of Carry Propagation on Partition Boundaries
Patent: 6,272,514 →
Application: 09/195,751 →
Method and Apparatus for Dynamic Partitionable Saturating Adder/Subtractor
Patent: 6,301,600 →
Application: 09/195,752 →
Method and Apparatus for Handling Partial Register Accesses
Patent: 6,334,183 →
Application: 09/195,757 →
Method and Apparatus That Enforces a Regional Memory Model in Hierarchical Memory Systems
Patent: 6,370,632 →
Application: 09/195,758 →
Method and Apparatus for Tlb Memory Ordering
Patent: 6,260,131 →
Application: 09/195,779 →
Method and Apparatus for 3-Stage 32-Bit Adder/Substractor
Patent: 6,269,387 →
Application: 09/206,463 →
Method and Apparatus for a 1 of 4 Shifter
Patent: 6,324,239 →
Application: 09/206,539 →
Method and Apparatus for an N-Nary Equality Comparator
Patent: 6,154,120 →
Application: 09/206,631 →
Method and Apparatus for N-Nary Incrementor
Patent: 6,347,327 →
Application: 09/206,830 →
Method and Apparatus for Transforming Pseudorandom Binary Test Patterns into Test Stimulus Patterns Appropriate for Circuits Having 1 of N Encoded Inputs
Patent: 6,295,622 →
Application: 09/206,900 →
Method and Apparatus for Transforming Pseudorandom Binary Patterns into Test Stimulus Patterns Appropriate for Circuits Having 1 of N Encoded Inputs
Patent: 6,429,795 →
Application: 09/206,905 →
Method and Apparatus for an N-Nary Magnitude Comparator
Patent: 6,216,147 →
Application: 09/206,906 →
Method and Apparatus for 1 of 4 Register File Design
Patent: 6,104,642 →
Application: 09/207,806 →
A Method and Apparatus for a Logic Circuit with Constant Power Consumption
Patent: 6,107,835 →
Application: 09/209,207 →
Dynamic 3-Level Partial Result Merge Adder
Patent: 6,334,136 →
Application: 09/209,935 →
Method and Apparatus for a N-Nary Logic Circuit Using Capacitance Isolation
Patent: 6,124,735 →
Application: 09/209,967 →
Method and Apparatus for a Logic Circuit Design Tool
Patent: 6,345,381 →
Application: 09/210,024 →
Method and Apparatus for N-Nary Hardware Description Language
Patent: 6,289,497 →
Application: 09/210,408 →
Method and Apparatus for N-Nary Logic Circuit Design Tool with Precharge Circuit Evaluation
Patent: 6,367,065 →
Application: 09/210,410 →
Method and Apparatus for Multi-Bit Register Cell
Patent: 6,115,294 →
Application: 09/291,659 →
Method and Apparatus That Supports Multiple Assignment Code
Patent: 6,360,315 →
Application: 09/373,516 →
Software System Build Method and Apparatus That Supports Multiple Users in a Software Development Environment
Patent: 6,457,170 →
Application: 09/373,840 →
Method and Apparatus for Object Cache Registration and Maintenance in a Networked Software Development Environment
Patent: 6,438,743 →
Application: 09/374,588 →
Method and Apparatus for a 5:2 Carry-Save-Adder (Csa)
Patent: 6,567,835 →
Application: 09/398,618 →
Multiple-State Simulation for Non-Binary Logic
Patent: 6,604,065 →
Application: 09/405,474 →
Software Modeling of Logic Signals Capable of Holding More Than Two Values
Patent: 7,031,897 →
Application: 09/405,618 →
Method and Apparatus That Reports Multiple Status Events with a Single Monitor
Patent: 6,594,803 →
Application: 09/406,016 →
Method and Apparatus for a Monitor That Detects and Reports a Status Event to a Database
Patent: 6,889,180 →
Application: 09/406,017 →
Method and Apparatus for an N-Nary Logic Circuit
Patent: 6,252,425 →
Application: 09/458,763 →
Method and Apparatus for a Ram Circuit Having N-Nary Output Interface
Patent: 6,181,596 →
Application: 09/458,766 →
Method and Apparatus for Scan of Synchronized Dynamic Logic Using Embedded Scan Gates
Patent: 6,415,405 →
Application: 09/468,759 →
Method and Apparatus for a Special Stress Mode for N-Nary Logic That Initializes the Logic into a Functionally Illegal State
Patent: 6,412,085 →
Application: 09/468,760 →
Dynamic Logic Scan Gate Method and Apparatus
Patent: 6,271,683 →
Application: 09/468,972 →
Method for Manufacturing Phosphor Layer for Image Display Apparatus
Patent: 6,455,213 →
Application: 09/477,345 →
Method and Apparatus for Pre-Branch Instruction
Patent: 6,622,240 →
Application: 09/496,008 →
Dynamic adjustment of the clock rate in logic circuits
Patent: 6,349,387 →
Application: 09/503,397 →
Rounding Anticipator for Floating Point Operations
Patent: 6,557,021 →
Application: 09/527,653 →
Leading Zero/One Anticipator for Floating Point Operations
Patent: 6,499,044 →
Application: 09/546,412 →
Method and apparatus for logic synchronization
Patent: 6,268,746 →
Application: 09/586,638 →
Method and Apparatus for a N-Nary Logic Circuit Using Capacitance Isolation
Patent: 6,571,378 →
Application: 09/587,729 →
Dynamic Logic Scan Gate Method and Apparatus
Patent: 6,745,357 →
Application: 09/901,411 →
Publication: US 2001/0039635
Random Number Indexing Method and Apparatus That Eliminates Software Call Sequence Dependency
Patent: 6,728,654 →
Application: 09/965,945 →
Publication: US 2003/0023396
Grid That Tracks the Occurrence of a N-Dimensional Matrix of Combinatorial Events in a Simulation Using a Linear Index
Patent: 7,099,812 →
Application: 09/966,049 →
Publication: US 2002/0040285
Generation of Route Rules
Patent: 6,732,346 →
Application: 10/155,042 →
Publication: US 2002/0178428
Rearranging Data Between Vector and Matrix Forms in a Simd Matrix Processor
Patent: 6,898,691 →
Application: 10/164,040 →
Publication: US 2002/0198911
Software program that transforms an N-dimensional matrix of integers to a linear index
Application: 10/177,448 →
Publication: US 2003/0122584
Monitor Manager That Creates and Executes State Machine-Based Monitor Instances in a Digital Simulation
Patent: 7,346,484 →
Application: 10/177,527 →
Publication: US 2003/0046645
Static Transmisstion of FAST14 Logic 1-of-N Signals
Patent: 6,714,045 →
Application: 10/186,770 →
Publication: US 2003/0042935
Static Storage Element for Dynamic Logic
Patent: 6,956,406 →
Application: 10/187,879 →
Publication: US 2003/0110404
Null Value Propagation for FAST14 Logic
Patent: 7,053,664 →
Application: 10/300,289 →
Publication: US 2004/0006753
Physical Realization of Dynamic Logic Using Parameterized Tile Partitioning
Patent: 7,219,326 →
Application: 10/738,278 →
Publication: US 2005/0060128
Expansion Syntax
Patent: 7,299,461 →
Application: 10/738,281 →
Publication: US 2004/0139423
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Feb 5, 1998
From: BLOMGREN, JAMES S.; POTTER, TERENCE M.; HOME, STEPHEN C.; SENINGEN, MICHAEL R.
To: EVSX, INC., A CORPORATION OF TEXAS
Reel/Frame 008969/0945 →
Assignment of Assignor's Interest Feb 5, 1998
From: BLOMGREN, JAMES S.; POTTER, TERENCE M.; HORNE, STEPHEN C.; SENINGEN, MICHAEL R.
To: EVSX, INC.
Reel/Frame 009001/0769 →
Assignment of Assignor's Interest Feb 5, 1998
From: BLOMGREN, JAMES S.; POTTER, TERENCE M.; HORNE, STEPHEN C.; SENINGEN, MICHAEL R.
To: EVSX, INC., A CORPORATION OF TEXAS
Reel/Frame 008978/0688 →
Assignment of Assignor's Interest May 6, 1998
From: SENINGEN, MICHAEL R.; BLOMGREN, JAMES S.; POTTER, TERENCE M.
To: EVSX, INC.
Reel/Frame 009166/0420 →
Assignment of Assignor's Interest May 6, 1998
From: SENINGEN, MICHAEL R.; BLOMGREN, JAMES S.
To: EVSX, INC.
Reel/Frame 009212/0956 →
Assignment of Assignor's Interest Jul 22, 1998
From: BROOKS, JEFFREY S.; BLOMGREN, JAMES S.
To: EVSX, INC.
Reel/Frame 009343/0272 →
Assignment of Assignor's Interest Jul 22, 1998
From: BROOKS, JEFFREY S.; BLOMGREN, JAMES S.
To: EVSX, INC.
Reel/Frame 009358/0618 →
Assignment of Assignor's Interest Jul 22, 1998
From: BROOKS, JEFFREY S.; BLOMGREN, JAMES S.
To: EVSX, INC. A CORP. OF TEXAS
Reel/Frame 009343/0584 →
Assignment of Assignor's Interest Jul 22, 1998
From: BROOKS, JEFFREY S.; BLOMGREN, JAMES S.
To: EVSX, INC.
Reel/Frame 009343/0352 →
Assignment of Assignor's Interest Jul 24, 1998
From: BLOOMGREN, JAMES S.
To: EVSX, INC.
Reel/Frame 009357/0864 →
Assignment of Assignor's Interest Jul 28, 1998
From: BLOMGREN, JAMES S.; POTTER, TERRENCE M.
To: EVSX, INC.
Reel/Frame 009361/0766 →
Assignment of Assignor's Interest Sep 9, 1998
From: HORNE, STEPHEN C.; SENINGEN, MICHAEL R.
To: EVSX, INC., A CORPORATION OF TEXAS
Reel/Frame 009452/0688 →
Assignment of Assignor's Interest Sep 9, 1998
From: HORNE, STEPHEN C.; SENINGEN, MICHAEL R.; BLOMGREN, JAMES S.
To: EVSX, INC., A CORPORATION OF TEXAS
Reel/Frame 009454/0352 →
Assignment of Assignor's Interest Sep 9, 1998
From: HORNE, STEPHEN C.; SENINGEN, MICHAEL R.; BLOMGREN, JAMES S.
To: EVSX, INC.
Reel/Frame 009450/0634 →
Assignment of Assignor's Interest Sep 10, 1998
From: PETRO, ANTHONY M.; BLOMGREN, JAMES S.
To: EVSX, INC.
Reel/Frame 009450/0874 →
Assignment of Assignor's Interest Sep 10, 1998
From: PETRO, ANTHONY M.; BLOMGREN, JAMES S.
To: EVSX, INC.
Reel/Frame 009475/0224 →
Assignment of Assignor's Interest Sep 10, 1998
From: PETRO, ANTHONY M.; BLOMGREN, JAMES S.
To: EVSX, INC., A CORPORATION OF TEXAS
Reel/Frame 009450/0878 →
Assignment of Assignor's Interest Sep 10, 1998
From: PETRO, ANTHONY M.; BLOMGREN, JAMES S.
To: EVSX, INC., A CORPORATION OF TEXAS
Reel/Frame 009451/0095 →
Assignment of Assignor's Interest Oct 9, 1998
From: BLOMGREN, JAMES S.; POTTER, TERRENCE M.
To: EVSX, INC.
Reel/Frame 009510/0971 →
Assignment of Assignor's Interest Oct 27, 1998
From: POTTER, TERENCE M.; BLOMGREN, JAMES S.; PETRO, ANTHONY M.; HORNE, STEPHEN C.
To: EVSX, INC.
Reel/Frame 009558/0296 →
Assignment of Assignor's Interest Oct 27, 1998
From: POTTER, TERENCE M.; BLOMGREN, JAMES S.; PETRO, ANTHONY M.; HORNE, STEPHEN C.
To: EVSX, INC.
Reel/Frame 009548/0011 →
Assignment of Assignor's Interest Oct 27, 1998
From: POTTER, TERENCE M.; BLOMGREN, JAMES S.; PETRO, ANTHONY M.; HORNE, STEPHEN C.
To: EVSX, INC.
Reel/Frame 009546/0747 →
Assignment of Assignor's Interest Oct 28, 1998
From: BLOMGREN, JAMES S.; POTTER, TERENCE M.; BROOKS, JEFFREY S.
To: EVSX, INC., A CORPORATION OF TEXAS
Reel/Frame 009548/0944 →
Assignment of Assignor's Interest Oct 28, 1998
From: BLOMGREN, JAMES S.; POTTER, TERENCE M.; BROOKS, JEFFREY S.
To: EVSX, INC., A CORPORATION OF TEXAS
Reel/Frame 009557/0892 →
Assignment of Assignor's Interest Nov 3, 1998
From: BLOMGREN, JAMES S.
To: EVSX, INC.
Reel/Frame 009574/0500 →