Software modeling of logic signals capable of holding more than two values
A method of efficiently simulating logic designs comprising signals that are capable of having more than two unique decimal values and one or more unique drive states, such as designs based upon the new N-nary logic design style, is disclosed. The present invention includes a signal model that models N-nary signal value, drive strength, and signal definition information in a specific format that supports the ability of the simulator to simulate the operation of the N-nary logic gates such as adders, buffers, and multiplexers by arithmetically and logically manipulating the unique decimal values of the N-nary signals. The simulator comprises an input logic signal model reader, an arithmetic/logical operator, an output logic signal model generator, and an output message generator that generates one or more output- or input-signal-specific output messages that pack relevant simulation data into a format optimized to the architecture of the simulation host.
1. A signal model used in an N-NARY logic simulation, comprising:
a signal value, said signal value further comprises the logic value of a nonbinary 1-of-N logic signal being modeled, wherein said logic value further comprises an integer greater than 1;
a signal strength, said signal strength further comprises the drive state of said nonbinary 1-of-N logic signal being modeled; and
a signal definition, said signal definition further comprises the defined or undefined status of said nonbinary 1-of-N logic signal being modeled.
2. The model of claim 1 , wherein said logic value further comprises an integer less than or equal to 31.
3. The model of claim 1 , wherein said signal strength further comprises one of the following: the high-impedance state, the weakly-driven state, the moderately-driven state, or the strongly-driven state.
4. A method that makes a signal model used in an N-NARY logic simulation, comprising:
assigning a signal value, said signal value further comprises the logic value of a nonbinary 1-of-N logic signal being modeled, wherein said logic value further comprises an integer greater than 1;
assigning a signal strength, said signal strength further comprises the drive state of said nonbinary 1-of-N logic signal being modeled; and
assigning a signal definition, said signal definition further comprises the defined or undefined status of said nonbinary 1-of-N logic signal being modeled.
5. The method of claim 4 , wherein said logic value further comprises an integer less than or equal to 31.
6. The method of claim 4 , wherein said signal strength further comprises one of the following: the high-impedance state, the weakly-driven state, the moderately-driven state, or the strongly-driven state.
7. A method that uses a signal model used in an N-NARY logic simulation, comprising:
reading a signal value, said signal value further comprises the logic value of a nonbinary 1-of-N logic signal being modeled, wherein said logic value further comprises an integer greater than 1;
reading a signal strength, said signal strength further comprises the drive state of said nonbinary 1-of-N logic signal being modeled;
reading a signal definition, said signal definition further comprises the defined or undefined status of said nonbinary 1-of-N logic signal being modeled; and
providing said signal value, said signal state, and said signal definition to the software-implemented simulation of the N-NARY logic design.
8. The method of claim 7 , wherein said logic value further comprises an integer less than or equal to 31.
9. The method of claim 7 , wherein said signal strength further comprises one of the following: the high-impedance state, the weakly-driven state, the moderately-driven state, or the strongly-driven state.
10. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method that uses a signal model used in an N-NARY logic simulation, comprising:
reading a signal value, said signal value further comprises the logic value of a nonbinary 1-of-N logic signal being modeled, wherein said logic value further comprises an integer greater than 1;
reading a signal strength, said signal strength further comprises the drive state of said nonbinary 1-of-N logic signal being modeled;
reading a signal definition, said signal definition further comprises the defined or undefined status of said nonbinary 1-of-N logic signal being modeled; and
providing said signal value, said signal state, and said signal definition to the software-implemented simulation of the N-NARY logic design.
11. The program storage device of claim 10 , wherein said logic value further comprises an integer less than or equal to 31.
12. The program storage device of claim 10 , wherein said signal strength further comprises one of the following: the high-impedance state, the weakly-driven state, the moderately-driven state, or the strongly-driven state.
13. A signal modeling system used in an N-NARY logic simulation, comprising:
a signal value, said signal value further comprises the logic value of a nonbinary 1-of-N logic signal being modeled, wherein said logic value further comprises an integer greater than 1;
a signal strength, said signal strength further comprises the drive state of said nonbinary 1-of-N logic signal being modeled; and
a signal definition, said signal definition further comprises the defined or undefined status of said nonbinary 1-of-N logic signal being modeled.
14. The system of claim 13 , wherein said logic value further comprises an integer less than or equal to 31.
15. The system of claim 13 , wherein said signal strength further comprises one of the following: the high-impedance state, the weakly-driven state, the moderately-driven state, or the strongly-driven state.