Granted Patent B1

US 6,889,180 · App. 09/406,017 · Granted May 3, 2005

Assignee: Intrinsity, Inc.

Abstract

Claims (42)

1. A monitor comprising software instructions, which when executed by a computer, causes the computer to detect a design verification event and reports a status event to a database, comprising:

a monitor declaration;

zero or more signal declarations wherein an individual signal declaration describes a signal having a signal name;

zero or more bus declarations wherein said bus declaration defines a bus that further comprises a set of signals that represents a single value determined by packing single bit values into a multibit variable;

one or more logic expressions that the monitor uses to evaluate whether the design verification event has occurred so that the monitor can return a status event; and wherein the signal is an N-Nary signal.

2. The monitor of claim 1 wherein the monitor reports the status event to a database.

3. The monitor of claim 1 further comprising a parser that translates the monitor into code that uses a standard computer language.

4. The monitor of claim 1 further comprising one or more computers that execute the code of the monitor.

5. A system that uses a monitor comprising software instructions, which when executed by a computer, causes the computer to detect a design verification event and reports a status event to a database, comprising:

a monitor declaration;

zero or more signal declarations wherein an individual signal declaration describes a signal having a signal name;

zero or more bus declarations wherein said bus declaration defines a bus that further comprises a set of signals that represents a single value determined by packing single bit values into a multibit variable;

one or more logic expressions that the monitor uses to evaluate whether the design verification event has occurred so that the monitor can return a status event; and wherein the signal is an N-Nary signal.

6. The system of claim 5 wherein the monitor reports the status event to a database.

7. The system of claim 5 further comprising a parser that translates the monitor into code that uses a standard computer language.

8. The system of claim 5 further comprising one or more computers that execute the code of the monitor.

9. A method that uses a monitor comprising software instructions, which when executed by a computer, causes the computer to detect a design verification event and reports a status event to a database, comprising:

providing a monitor declaration;

providing zero or more signal declarations wherein an individual signal declaration describes a signal having a signal name;

providing zero or more bus declarations wherein said bus declaration defines a bus that further comprises a set of signals that represents a single value determined by packing single bit values into a multibit variable;

providing one or more logic expressions;

evaluating said logic expressions to detect the design verification event so that the monitor can return a status event; and wherein the signal is an N-Nary signal.

10. The method of claim 9 wherein the monitor reports the status event to a database.

11. The method of claim 9 further comprising a parser that translates the monitor into code that uses a standard computer language.

12. The method of claim 9 further comprising one or more computers that execute the code of the monitor.

13. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method that uses a monitor comprising software instructions, which when executed by a computer, causes the computer to detect a design verification event and reports a status event to a database, comprising:

providing a monitor declaration;

providing zero or more signal declarations wherein an individual signal declaration describes a signal having a signal name;

providing one zero or more bus declarations wherein said bus declaration defines a bus that further comprises a set of signals that represents a single value determined by packing single bit values into a multibit variable;

providing one or more logic expressions;

evaluating said logic expressions to detect the design verification, event so that the monitor can return a status event; and wherein the signal is an N-Nary signal.

14. The program storage device of claim 13 wherein the monitor reports the status event to a database.

15. The program storage device of claim 13 further comprising a parser that translates the monitor into code that uses a standard computer language.

16. The program storage device of claim 13 further comprising one or more computers that execute the code of the monitor.

17. A method that provides a monitor comprising software instructions, which when executed by a computer causes the computer to detect a design verification event and reports a status event to a database, comprising:

providing a monitor declaration;

providing zero or more signal declarations wherein an individual signal declaration describes a signal having a signal name;

providing zero or more bus declarations wherein said bus declaration defines a bus that further comprises a set of signals that represents a single value determined by packing single bit values into a multibit variable;

providing one or more logic expressions that the monitor uses to evaluate whether the design verification event has occurred so that the monitor can return a status event; and wherein said signal is an N-Nary signal.

18. The method of claim 17 wherein the monitor reports the status event to a database.

19. The method of claim 17 further comprising a parser that translates the monitor into code that uses a standard computer language.

20. The method of claim 17 further comprising one or more computers that execute the code of the monitor.

Assignments (8)

Continuity (1)