Null value propagation for FAST14 logic
Power consumption in NDL designs utilizing FAST14 technology can be controlled via the introduction and propagation of null value 1-of-N signals in selected areas of the logic. A shared logic tree circuit, which might perform an arithmetic function or a multiplexing function, evaluates a 1-of-N input logic signal and produces a 1-of-N output logic signal having a null value if the input has a null value. A null value signal is defined as a valid multiwire 1-of-N signal used in NDL logic having N wires where N is greater than 2, where no one of the N wires of the 1-of-N signal is asserted when the NDL gate evaluates.
1. A NDL logic gate that propagates a null value, comprising:
a 1-of-N input logic signal having N input wires where N is greater than 2; and
a shared logic tree circuit having an evaluate state and a precharge state, said shared logic tree circuit evaluates said 1-of-N input logic signal and produces a 1-of-N output logic signal having N output wires where N is greater than 2;
wherein said 1-of-N output logic signal further comprises a null value signal having none of said N output wires asserted after said evaluate state if said 1-of-N input logic signal comprises a null value signal having none of said N input wires asserted during said evaluate state.
2. A method that makes an NDL logic gate that propagates a null value, comprising:
providing a 1-of-N input logic signal having N input wires where N is greater than 2; and
coupling a shared logic tree circuit having an evaluate state and a precharge state to said 1-of-N input logic signal, said shared logic tree circuit evaluates said 1-of-N input logic signal and produces a 1-of-N output logic signal having N output wires where N is greater than 2;
wherein said 1-of-N output logic signal further comprises a null value signal having none of said N output wires asserted after said evaluate state if said 1-of-N input logic signal comprises a null value signal having none of said N input wires asserted during said evaluate state.
3. A method that uses an NDL logic gate that propagates a null value, comprising:
receiving a 1-of N input logic signal having N input wires where N is greater than 2; and
producing a 1-of-N output logic signal having N output wires where N is greater than 2 by evaluating said 1-of-N input logic signal using a shared logic tree circuit having an evaluate state and a precharge state;
wherein said 1-of-N output logic signal further comprises a null value signal having none of said N output wires asserted after said evaluate state if said 1-of-N input logic signal comprises a null value signal having none of said N input wires asserted during said evaluate state.
4. A dependent claim according to claim 1 , 2 , or 3 wherein said shared logic tree circuit further comprises a circuit that performs an arithmetic function that either combines one or more data inputs to produce an output or manipulates one or more data inputs to produce an output.
5. A dependent claim according to claim 1 , 2 , or 3 wherein said shared logic tree circuit further comprises a multiplexer circuit that selects one or more data inputs to produce an output.
6. An NDL logic gate that propagates a null value, comprising:
a 1-of-N input logic signal having N input wires where N is greater than 2; and
a shared logic tree circuit having an evaluate state and a precharge state that receives said 1-of-N input logic signal and produces a 1-of-N output logic signal having N output wires where N is greater than 2, said shared logic tree circuit further consists of one of the following: a logic circuit that performs an arithmetic function that either combines one or more data inputs or manipulates one or more data inputs to produce said 1-of-N output logic signal, or a multiplexer circuit that selects one or more data inputs to produce said 1-of-N output logic signal;
wherein said 1-of-N output logic signal further comprises a first null value signal having none of said N output wires asserted after said evaluate state if said 1-of-N input logic signal comprises a second null value signal having none of said N input wires asserted during said evaluate state.
7. A method that makes an NDL logic gate that propagates a null value, comprising:
providing a 1-of-N input logic signal having N input wires where N is greater than 2; and
coupling a shared logic tree circuit having an evaluate state and a precharge state to said 1-of-N input logic signal, said shared logic tree circuit produces a 1-of-N output logic signal having N output wires where N is greater than 2, said shared logic tree circuit further consists of one of the following: a logic circuit that performs an arithmetic function that either combines one or more data inputs or manipulates one or more data inputs to produce said 1-of-N output logic signal, or a multiplexer circuit that selects one or more data inputs to produce said 1-of-N output logic signal;
wherein said 1-of-N output logic signal further comprises a first null value signal having none of said N output wires asserted after said evaluate state if said 1-of-N input logic signal comprises a second null value signal having none of said N input wires asserted during said evaluate state.
8. A method that uses an NDL logic gate that propagates a null value, comprising:
receiving a 1-of-N input logic signal having N input wires where N is greater than 2; and
producing a 1-of-N output logic signal having N output wires where N is greater than 2 using a shared logic tree circuit having an evaluate state and a precharge state that receives said 1-of-N input logic signal, said shared logic tree circuit further consists of one of the following: a logic circuit that performs an arithmetic function that either combines one or more data inputs or manipulates one or more data inputs to produce said 1-of-N output logic signal, or a multiplexer circuit that selects one or more data inputs to produce said 1-of-N output logic signal;
wherein said 1-of-N output logic signal further comprises a first null value signal having none of said N output wires asserted after said evaluate state if said 1-of-N input logic signal comprises a second null value signal having none of said N input wires asserted during said evaluate state.