Bonded wafer with metal silicidation
View Patent ↗A silicon-on-insulator integrated circuit comprises a handle die, a substantially continuous and unbroken silicide layer over the handle die, and a substantially continuous and unbroken first dielectric layer overlying one side of the silicide layer. A device silicon layer having an upper surface overlies the first dielectric layer, and a second dielectric layer on the handle die underlies the opposite side of the silicide layer. Interconnected transistors are disposed in and at the upper surface of the device silicon layer. A silicon-on insulator integrated circuit includes a handle die and a first dielectric layer formed on the handle die. A substantially continuous and unbroken silicide layer is formed on the first dielectric layer; the silicide layer has a controlled resistance and provides a diffusion barrier to impurities. A substantially continuous and unbroken second dielectric layer is disposed between the silicide layer and a device silicon layer, and trenches extend through the device silicon layer and silicide layer and separate the device silicon layer into islands, each having an underlying continuous silicide area. Interconnected transistors are disposed in and at an upper surface of the device silicon layer. A bonded wafer integrated circuit comprised a handle die and a homogeneous silicide layer bonded to the handle die. A device layer is bonded to the silicide layer, and interconnected transistors are disposed in and at a surface of device layer.
1. A silicon-on-insulator integrated circuit, comprising:
(a) a handle die;
(b) a substantially continuous silicide layer over said handle die,
(c) a substantially continuous first dielectric layer overlying one side of said silicide layer;
(d) a device silicon layer overlying said first dielectric layer, said device silicon layer having an upper surface;
(e) a second dielectric layer on said handle die underlying the opposite side of said silicide layer; and
(f) interconnected transistors in and at the upper surface of said device silicon layer.
2. The integrated circuit of claim 1 wherein said silicide layer comprises a diffusion barrier to impurities.
3. The integrated circuit of claim 1 further comprising:
(g) trenches extending through said device silicon layer and separating said dice silicon layer into islands.
4. A silicon-on insulator integrated circuit comprising:
(a) a handle die;
(b) a first dielectric layer formed on said handle die
(c) a substantially continuous silicide layer formed on said first dielectric layer, said silicide layer having a controlled resistance and providing a diffusion barrier to impurities;
(d) a substantially continuous second dielectric layer disposed between said silicide layer and a device silicon layer;
(e) trenches extending through said device silicon layer and silicide layer and separating said device silicon layer into islands each with an underlying continuous silicide area; and
(f) interconnected transistors in and at an upper surface of said device silicon layer.
5. The integrated circuit of claim 4 further comprising:
(g) trenches extending through at least one of said islands to said underlying silicide area, said trenches having dielectric sidewalls and containing conductive material in contact with said silicide area.
6. The integrated circuit of claim 5 wherein said islands have a thickness no greater than about 2 μm, and said conductive material is tungsten.