IP Library › Assignment 024445/0049
Patent Assignment
Reel/Frame 024445/0049

Release of Security Interest

Recorded: 2010-05-26 Pages: 66
Assignor
CREDIT SUISSE FIRST BOSTON
Executed: 2003-03-06
Assignee
INTERSIL CORPORATION
2401 PALM BAY ROAD NE, PALM BAY, FLORIDA, 32905
Covered Properties (374)
Current Mirror Circuit with Cascoded Transistors
Patent: 5,248,932 →
Application: 07/474,172 →
Digital Signal Processing Address Sequencer
Patent: 5,265,225 →
Application: 07/482,803 →
Mesfet for Dielectrically Isolated Integrated Circuits
Patent: 5,014,108 →
Application: 07/523,427 →
Band-Gap Reference
Patent: 5,081,410 →
Application: 07/529,548 →
Trench Conductor and Crossunder Architecture
Patent: 5,057,895 →
Application: 07/563,276 →
Fast Turn-Off of Thyristor Structure
Patent: 5,086,242 →
Application: 07/598,165 →
Stacked Configuration for Integrated Circuit Devices
Patent: 5,117,282 →
Application: 07/604,883 →
Method of Making Silicon Mesfet for Dielectrically Isolated Integrated Circuits
Patent: 5,306,650 →
Application: 07/606,193 →
Method and Apparatus for Testing Lead Bonds and Detecting Failure
Patent: 5,085,084 →
Application: 07/615,358 →
Direct Bonding of Copper to Aluminum Nitride Substrates
Patent: 5,418,002 →
Application: 07/632,876 →
Semiconductor Structure Within Di Islands Having Bottom Projection for Controlling Device Characteristics
Patent: 5,306,944 →
Application: 07/651,327 →
Level Shift Circuit with Common Mode Rejection
Patent: 5,105,099 →
Application: 07/663,224 →
Graded Collector for Inductive Loads
Patent: 5,311,054 →
Application: 07/674,147 →
Self-Aligned Channel Stop for Trench-Isolated Island
Patent: 5,248,894 →
Application: 07/679,182 →
Method of Laser Trimming
Patent: 5,096,850 →
Application: 07/689,624 →
Voltage Divider and Use as Bias Network for Stacked Transistors
Patent: 5,233,289 →
Application: 07/689,645 →
High Voltage Lateral Semiconductor Device
Patent: 5,264,719 →
Application: 07/705,509 →
Overvoltage Sensor with Hysteresis
Patent: 5,335,132 →
Application: 07/716,488 →
Low Offset Unity Gain Buffer Amplifier
Patent: 5,218,321 →
Application: 07/717,347 →
High Speed Differential Comparator
Patent: 5,332,931 →
Application: 07/720,082 →
Decimation Circuit Employing Multiple Memory Data Shifting Section and Multiple Arithmetic Logic Unit Section
Patent: 5,206,821 →
Application: 07/724,206 →
High Voltage Protection Using Scrs
Patent: 5,359,211 →
Application: 07/732,475 →
Buried Zener Diode Having Auxiliary Zener Junction Access Path
Patent: 5,241,213 →
Application: 07/739,133 →
Thin, Dielectrically Isolated Island Resident Transistor Structure Having Low Collector Resistance
Patent: 5,327,006 →
Application: 07/755,314 →
Resistor Structure and Method of Fabrication
Patent: 5,200,733 →
Application: 07/769,209 →
Noncanonic Fully Systolic Lms Adaptive Architecture
Patent: 5,450,339 →
Application: 07/774,620 →
Fold and Decimate Filter Architecture
Patent: 5,258,939 →
Application: 07/774,628 →
Bimos Current Driver Circuit
Patent: 5,262,689 →
Application: 07/781,626 →
Analog-To-Digital Converter and Method of Fabrication
Patent: 5,369,309 →
Application: 07/785,325 →
Differential Voltage Follower
Patent: 5,382,916 →
Application: 07/785,395 →
Input Bias Current Compensation for a Comparator
Patent: 5,128,564 →
Application: 07/790,677 →
Print Band Cleaner
Patent: 5,220,868 →
Application: 07/791,853 →
Symmetric, High Speed, Voltage Switching Circuit Possessing Reverse Viltage Application Immunity
Patent: 5,302,859 →
Application: 07/791,856 →
Slew Control in Current Feedback Amplifiers
Patent: 5,179,355 →
Application: 07/793,641 →
High Speed Bipolar Digital Logic Gate Architecture
Patent: 5,229,661 →
Application: 07/806,074 →
Method of Manufacturing a Multi-Layered I C Packaging Assembly
Patent: 5,228,192 →
Application: 07/825,133 →
Reduced Semiconductor Size Package
Patent: 5,434,357 →
Application: 07/831,252 →
Selective Recrystallization to Reduce P-Channel Transistor Leakage in Silicon-on-Sapphire Cmos Radiation Hardened Integrated Circuits
Patent: 5,298,434 →
Application: 07/832,694 →
Wafer Bonding Process Emplyoing Liquid Oxidant
Patent: 5,266,135 →
Application: 07/834,439 →
Telephone Subscriber Line Circuit, Components and Methods
Patent: 5,745,563 →
Application: 07/840,547 →
Method and Device in Which Bottoming of a Well in a Dielectrically Isolated Island Is Assured
Patent: 5,270,569 →
Application: 07/840,548 →
Electrically Programmable Memory Cell
Patent: 5,640,346 →
Application: 07/846,286 →
Laser Trimmed Integrated Circuit
Patent: 5,235,205 →
Application: 07/852,541 →
Method of Forming Island with Polysilicon-Filled Trench Isolation
Patent: 5,217,919 →
Application: 07/854,805 →
Soi Cmos Device Having Differentially Doped Body Extension for Providing Improved Backside Leakage Channel Stop
Patent: 5,293,052 →
Application: 07/855,834 →
Power Driver Circuit
Patent: 5,504,449 →
Application: 07/865,868 →
Integration of High Voltage Lateral Mos Devices in Low Voltage Cmos Architecture Using Cmos-Compatible Process Steps
Patent: 5,322,804 →
Application: 07/882,070 →
Soi Wafer with Sige
Patent: 5,218,213 →
Application: 07/891,052 →
Method of Fabricating Soi Water with Sige as an Etchback Film in a Besoi Process
Patent: 5,240,876 →
Application: 07/891,910 →
Precision Voltage Reference Circuit
Patent: 5,300,877 →
Application: 07/904,848 →
Seu-Immune Latch for Gate Array, Standard Cell, and Other Asic Applications
Patent: 5,311,070 →
Application: 07/905,015 →
Reduced Temperature Suppression of Volatilization of Photoexcited Halogen Reaction Products from Surface of Silicon Wafer
Patent: 5,352,327 →
Application: 07/911,902 →
Gas Phase Chemical Reduction of Metallic Branding Layer of Electronic Circuit Package for Deposition of Branding Ink
Patent: 5,279,850 →
Application: 07/913,844 →
Trench Conductor and Crossunder Architecture
Patent: 5,283,461 →
Application: 07/916,198 →
Bicmos Devices
Patent: 5,856,695 →
Application: 07/917,635 →
Breakdown Diode Structure
Patent: 5,448,100 →
Application: 07/919,001 →
Bonded Wafer Processing
Patent: 5,362,667 →
Application: 07/921,197 →
Formation of Dual Polarity Source/Drain Extensions in Lateral Complementary Channel Mos Architectures
Patent: 5,338,960 →
Application: 07/925,077 →
Process for Forming Twin Well Cmos Integrated Circuits
Patent: 5,247,199 →
Application: 07/928,992 →
Quadrature Filter with Real Conversion
Patent: 5,515,402 →
Application: 07/930,072 →
Decimation Filter and Method
Patent: 5,455,782 →
Application: 07/930,169 →
Digital Down Converter and Method
Patent: 5,493,581 →
Application: 07/930,170 →
Current Driver Having Voltage Transition Failure-Based Short Circuit Protecton Circuit
Patent: 5,428,492 →
Application: 07/930,737 →
Sine/Cosine Generator and Method
Patent: 5,276,633 →
Application: 07/930,926 →
Semiconductor Rom Device and Method
Patent: 5,440,506 →
Application: 07/930,930 →
Method for Forming Recessed Oxide Isolation Containing Deep and Shallow Trenches
Patent: 5,382,541 →
Application: 07/935,765 →
Circuit for Providing a Current Proportional to Absolute Temperature
Patent: 5,334,929 →
Application: 07/935,830 →
Comparator Amplifier
Patent: 5,287,068 →
Application: 07/936,596 →
Stress Relief Technique of Removing Oxide from Surface of Trench- Patterned Semiconductor-on-Insulator Structure
Patent: 5,270,265 →
Application: 07/939,115 →
Bonded Wafer Processing with Metal Silicidation
Patent: 5,387,555 →
Application: 07/939,786 →
Inductive Load Dump Circuit
Patent: 5,347,169 →
Application: 07/941,736 →
Decimating Filter
Patent: 5,341,335 →
Application: 07/945,674 →
Reduction of Bipolar Gain and Improvement in Snap-Back Sustaining Voltage in Soi Field Effect Transistor
Patent: 5,315,144 →
Application: 07/947,177 →
Method for Forming Semiconductor Electrical Contacts Using Metal Foil and Thermocompression Bonding
Patent: 5,206,186 →
Application: 07/950,553 →
Non-Linear Operational Transconductance Amplifier
Patent: 5,307,023 →
Application: 07/962,309 →
Resource Access Security System for Controlling Access to Resources of a Data Processing System
Patent: 5,469,556 →
Application: 07/972,510 →
Plural - Bit Recoding Multiplier
Patent: 5,262,976 →
Application: 07/973,932 →
Complementary Analog Multiplier Circuits with Differential Ground Referenced Outputs and Switching Capability
Patent: 5,389,840 →
Application: 07/974,129 →
Amplifier System for Low Level Sensor Signal
Patent: 5,406,223 →
Application: 07/979,209 →
Amplifier with High Common Mode Rejection
Patent: 5,287,071 →
Application: 07/980,570 →
Static Electricity Dispersant
Patent: 5,289,336 →
Application: 07/984,003 →
Electrostatic Discharge Protection
Patent: 5,416,351 →
Application: 07/984,187 →
Level Shifter Circuit
Patent: 5,341,047 →
Application: 07/991,094 →
Improved Sigma-Delta Type Analog-Digital Converter and Method
Patent: 5,345,236 →
Application: 07/993,585 →
Decoupling Tool Mechanism for Electrical Connectors
Patent: 5,312,262 →
Application: 07/995,442 →
Spiral Edge Passivation Structure for Semiconductor Devices
Patent: 5,382,825 →
Application: 08/001,752 →
Direct Thermocompression Bonding for Thin Electronic Power Chips
Patent: 5,304,847 →
Application: 08/007,300 →
Circuit for Introducing Hysterisis
Patent: 5,334,883 →
Application: 08/012,595 →
High Speed Differential Comparator
Patent: 5,329,187 →
Application: 08/018,619 →
Circuit and Method for Extending the Safe Operating Area of a Bjt
Patent: 5,357,089 →
Application: 08/023,117 →
Bonded Wafer Process Incorporating Diamond Insulator
Patent: 5,272,104 →
Application: 08/029,860 →
Curing of a Tungsten Filament in an Ion Implanter
Patent: 5,370,568 →
Application: 08/030,980 →
Low Input Resistance Current-Mode Feedback Operational Amplifier Input Stage
Patent: 5,351,012 →
Application: 08/041,936 →
An Integrated Circuit with Improved Reverse Bias Breakdown
Patent: 5,373,183 →
Application: 08/053,244 →
Low Input Resistance Amplifier Stage
Patent: 5,352,989 →
Application: 08/062,810 →
Method of Making Intergrated Circuit Structure with Narrow Line Widths
Patent: 5,639,688 →
Application: 08/066,355 →
Biasing of Island-Surrounding Material to Suppress Reduction of Breakdown Voltage Due to Field Plate Acting on Buried Layer/Island Junction Between High and Low Impurity Concentration Regions
Patent: 5,744,851 →
Application: 08/066,697 →
Integrated Circuit Thermal Sensor
Patent: 5,359,236 →
Application: 08/066,854 →
Voltage Divider and Use as Bias Network for Stacked Transistors
Patent: 5,493,207 →
Application: 08/071,795 →
Process for Forming Twin Well Cmos Integrated Circuits
Patent: 5,429,958 →
Application: 08/080,744 →
Differential Amplifier with Hysteresis
Patent: 5,367,211 →
Application: 08/082,546 →
Low Voltage Rf Amplifier and Mixer with Single Bias Block and Method
Patent: 5,809,410 →
Application: 08/090,617 →
Fast Charging Mos Capacitor Structure for High Magnitude Voltage of Either Positive or Negative Polarity
Patent: 5,341,009 →
Application: 08/090,978 →
Method and Device in Which Bottoming of a Well in a Dielectrically Isolated Island Is Assured
Patent: 5,438,221 →
Application: 08/091,819 →
Analog Multiplexer
Patent: 5,352,987 →
Application: 08/095,285 →
Complementary Gain Control Circuit
Patent: 5,374,898 →
Application: 08/099,701 →
Self-Aligned Channel Stop for Trench-Isolated Island
Patent: 5,436,189 →
Application: 08/106,160 →
Method for Interactively Tailoring Topography of Integrated Circuit Layout in Accordance with Electromigration Model-Based Minimum Width Metal and Contact/via Rules
Patent: 5,581,475 →
Application: 08/106,251 →
Sub-Micron Bonded Soi by Trench Planarization
Patent: 5,585,661 →
Application: 08/108,358 →
Current Mirror with Error Correction
Patent: 5,321,371 →
Application: 08/115,430 →
Fill and Etchback Process Using Dual Photoresist Sacrificial Layer and Two-Step Etching Process for Planarizing Oxide-Filled Shallow Trench Structure
Patent: 5,516,625 →
Application: 08/118,063 →
Methods for Forming a Transistor Having an Emitter with Enhanced Efficiency
Patent: 5,395,774 →
Application: 08/123,157 →
Die Separation Method for Silicon on Diamond Circuit Structures
Patent: 5,552,345 →
Application: 08/125,411 →
High Frequency Analog Transistors, Method of Fabrication and Circuit Implementation
Patent: 5,668,397 →
Application: 08/131,369 →
Resistance-Measurement Based Arrangement for Monitoring Integrity of Travel Path Ground Link in Electronic Components Handling Apparatus
Patent: 5,576,695 →
Application: 08/135,092 →
Method of Manufacture of Multi-Cell Integrated Circuit Architecture
Patent: 5,561,607 →
Application: 08/135,093 →
Wafer Bonding Using Trapped Oxidizing Vapor
Patent: 5,334,273 →
Application: 08/137,293 →
Synchronizing Signal Active Filter and Method
Patent: 5,528,303 →
Application: 08/146,598 →
Differential Analog Memory Cell and Method for Adjusting Same
Patent: 5,430,670 →
Application: 08/148,297 →
Selective Recrystallization to Reduce P-Channel Transistor Leakage in Silicon-on-Sapphire Cmos Radiation Hardened Integrated Circuits
Patent: 5,391,903 →
Application: 08/171,280 →
Fail-Safe Mos Shutdown Circuitry
Patent: 5,574,609 →
Application: 08/180,267 →
Voltage Independent Symmetrical Current Source with Cross-Coupled Transistors
Patent: 5,446,368 →
Application: 08/180,666 →
Trench Resistor Architecture
Patent: 5,466,963 →
Application: 08/180,737 →
Method for Providing a Silicon and Diamond Substrate Having a Carbon to Silicon Transition Layer and Apparatus Thereof
Patent: 5,526,768 →
Application: 08/190,998 →
Method of Making an Improved Graded Collector for Inductive Loads
Patent: 5,397,714 →
Application: 08/191,963 →
Differential Voltage Monitor Using a Bridge Circuit with Resistors on and Off an Integrated Circuit
Patent: 5,583,442 →
Application: 08/192,398 →
Plasma Cleaning Method for Improved Ink Brand Permanency on Ic Packages with Metallic Parts
Patent: 5,451,263 →
Application: 08/195,667 →
Esd Protection Using Scr Clmaping
Patent: 5,574,618 →
Application: 08/198,002 →
Current Mirror with Saturation Limiting
Patent: 5,508,551 →
Application: 08/204,710 →
Current Rise and Fall Time Limited Voltage Follower
Patent: 5,420,499 →
Application: 08/204,711 →
Reverse Current Flow Prevention in a Diffused Resistor
Patent: 5,608,259 →
Application: 08/204,718 →
Active Folded Cascode
Patent: 5,469,104 →
Application: 08/218,726 →
Integration of High Voltage Lateral Mos Devices in Low Voltage Cmos Architecture Using Cmos-Compatible Process Steps
Patent: 5,541,435 →
Application: 08/227,157 →
Digital Baseband to If Conversion in Cellular Base Stations
Patent: 5,519,732 →
Application: 08/235,979 →
Varactor Compensation in Amplifier Circuits
Patent: 5,420,542 →
Application: 08/242,946 →
Input Stage Improvement for Current Feedback Amplifiers
Patent: 5,418,495 →
Application: 08/245,683 →
Silicon on Diamond Circuit Structure
Patent: 5,561,303 →
Application: 08/248,844 →
High Voltage Protection Using Scrs
Patent: 5,670,799 →
Application: 08/253,287 →
Process for Manufacturing a Multi-Port Adhesive Dispensing Tool
Patent: 5,423,889 →
Application: 08/265,355 →
Current Follower with Zero Input Impedance
Patent: 5,614,867 →
Application: 08/266,567 →
Impedance Setting Circuit for a Slic
Patent: 5,515,434 →
Application: 08/267,434 →
Ground Key Detector for a Slic
Patent: 5,515,417 →
Application: 08/267,436 →
Integrated Ringer Relay Circuit and Method
Patent: 5,517,565 →
Application: 08/269,133 →
High Speed a/D Converter and Slew Controlled Pulse Detector
Patent: 5,808,489 →
Application: 08/269,470 →
Graphical Display Discriminant Factor Indicator for Anomaly Identification in Semiconductor Manufacture Batch Process
Patent: 5,450,326 →
Application: 08/271,292 →
Cmos Integrated Circuit Architecture Incorporating Deep Implanted Emitter Region to Form Auxiliary Bipolar Transistor
Patent: 6,350,640 →
Application: 08/276,290 →
Method of Making Contact Regions for Narrow Trenches in Semiconductor Devices
Patent: 5,622,890 →
Application: 08/279,027 →
Analog-To-Digital Converter and Reference Voltage Circuitry
Patent: 5,471,131 →
Application: 08/287,763 →
Bonded Wafer Processing
Patent: 5,517,047 →
Application: 08/287,773 →
Class Ab Complementary Output Stage
Patent: 5,475,343 →
Application: 08/290,362 →
Trench Isolation Stress Relief
Patent: 5,448,102 →
Application: 08/292,588 →
High Speed Comparator
Patent: 5,541,538 →
Application: 08/299,741 →
Video Scaling Method and Device
Patent: 5,574,572 →
Application: 08/301,622 →
Half-Band Filter and Method
Patent: 5,548,542 →
Application: 08/304,433 →
Method for Formation of a Well in a Dielectrically Isolated Island
Patent: 5,602,054 →
Application: 08/309,573 →
Programmable Element in Barrier Metal Device
Patent: 5,648,678 →
Application: 08/310,280 →
Structure and Tailoring Effective Resistivity of a Sipos Layer by Patterning and Control of Dopant Introduction
Patent: 5,637,908 →
Application: 08/314,489 →
A Voltage Controlled Amplifier Which Reduces Differential Gain
Patent: 5,469,106 →
Application: 08/328,701 →
Ultra High Gain Amplifier
Patent: 5,479,133 →
Application: 08/328,848 →
Sigma-Delta Analog to Digital Converter with Three Point Calibration Apparatus and Method
Patent: 5,598,157 →
Application: 08/331,015 →
Low Inductance Conductor Topography for Mosfet Circuit
Patent: 5,569,957 →
Application: 08/332,300 →
Method for Making Ohmic Contact to Lightly Doped Islands from a Silicide Buried Layer and Applications
Patent: 5,643,821 →
Application: 08/336,768 →
Method for Forming Relessed Oxide Isolation Containing Deep and Shallow Trenches
Patent: 5,504,033 →
Application: 08/339,966 →
Differential Longitudinal Amplifier for a Subscriber Line Interface Circuit
Patent: 5,649,009 →
Application: 08/340,342 →
Multiport Memory and Method
Patent: 5,563,834 →
Application: 08/345,689 →
Multiport Memory and Method
Patent: 5,586,072 →
Application: 08/346,178 →
Bonded Wafer Processing with Metal Silicidation
Patent: 5,569,620 →
Application: 08/351,933 →
Switch Controller and Method
Patent: 5,636,274 →
Application: 08/372,118 →
Current Mode Ring Trip Detector
Patent: 5,671,272 →
Application: 08/380,409 →
Circuit and Method for Loopback Test and on-Hook Transmission Integrated in a Telephone Subscriber Line Interface Circuit
Patent: 5,659,570 →
Application: 08/380,411 →
Filter with Reduced Element Ratings and Method
Patent: 5,572,162 →
Application: 08/380,412 →
Method and Circuit for Failsafe Switch-Hook Detection During Fault in a Telephone System
Patent: 5,812,658 →
Application: 08/380,413 →
Configuration Independent Auto-Biasing of Bipolar Transistor
Patent: 5,625,566 →
Application: 08/382,346 →
High Voltage, Junction Isolation Semiconductor Device Haivng Dual Conductivity Tape Buried Regions and Its Process of Manufacture
Patent: 5,567,978 →
Application: 08/383,261 →
Direct Etch for Thin Film Resistor Using a Hard Mask
Patent: 5,547,896 →
Application: 08/387,233 →
Analog-To-Digital Converter
Patent: 5,481,129 →
Application: 08/391,490 →
Method of Scaling the Outputs of a Binary Counter
Patent: 5,526,392 →
Application: 08/395,590 →
Multiple Use Timer and Method for Pulse Width Generation, Echo Failure Detection, and Receive Pulse Width Measurement
Patent: 5,661,736 →
Application: 08/395,591 →
Crc Generation and Detection Method
Patent: 5,724,370 →
Application: 08/395,814 →
Modification of Timing in an Emulator Circuit and Method
Patent: 5,678,030 →
Application: 08/395,863 →
Zero Phase Error Switched-Capacitor Phase Locked Loop Filter
Patent: 5,659,269 →
Application: 08/402,381 →
Process for Doping Two Levels of a Double Poly Bipolar Transistor After Formation of Second Poly Layer
Patent: 5,614,422 →
Application: 08/405,660 →
Digital Component Testing Apparatus and Method
Patent: 5,644,309 →
Application: 08/419,610 →
Method of Forming Dummy Island Capacitor
Patent: 5,602,052 →
Application: 08/427,231 →
Bonded Wafer Processing with Oxidative Bonding
Patent: 5,849,627 →
Application: 08/430,312 →
Multi-Channel Sigma-Delta a/D Converters with Improved Throughput
Patent: 5,617,090 →
Application: 08/438,251 →
Bimos Driver Circuit and Method
Patent: 5,576,654 →
Application: 08/441,726 →
Bonded Wafer and Method of Fabrication Thereof
Patent: 5,603,779 →
Application: 08/443,242 →
Semiconductor Wafer Having Slices and Limited Scribe Areas for Implementing Die
Patent: 5,656,851 →
Application: 08/443,623 →
Sense Amplifier for a Multiport Memory and Method
Patent: 5,650,971 →
Application: 08/450,878 →
Rom Cell for a Multiport Memory and Method
Patent: 5,544,095 →
Application: 08/450,879 →
Method of Forming P-Type Islands Over P-Type Buried Layer
Patent: 5,633,180 →
Application: 08/456,727 →
Phase Generator
Patent: 5,570,392 →
Application: 08/456,859 →
Fixed Coefficient High Decimation Filter
Patent: 5,617,344 →
Application: 08/457,234 →
Method of Manufacturing a Semiconductor Accelerometer
Patent: 5,656,512 →
Application: 08/457,643 →
Integrated Circuit Method for and Structure with Narrow Line Widths
Patent: 5,773,891 →
Application: 08/460,993 →
Integrated Circuit with Coaxial Isolation and Method
Patent: 5,814,889 →
Application: 08/461,037 →
Surface Mountable Integrated Circuit with Conductive Vias
Patent: 5,608,264 →
Application: 08/461,643 →
Method of Bonding Wafers Having Vias Including Conductive Material
Patent: 5,646,067 →
Application: 08/461,951 →
Method of Fabrication of Surface Mountable Integrated Circuits
Patent: 5,618,752 →
Application: 08/462,171 →
A True/Complementer for a Half-Band Filter
Patent: 5,574,671 →
Application: 08/462,684 →
High Frequency Analog Transistors, Method of Fabrication and Circuit Implementation
Patent: 5,807,780 →
Application: 08/462,851 →
Method of Increasing Maximum Terminal Voltage of a Semiconductor Device
Patent: 5,665,634 →
Application: 08/463,560 →
High Efficiency Quasi-Vertical Dmos in Cmos or Bicmos Process
Patent: 5,777,362 →
Application: 08/474,559 →
Method of Making an Integration of High Voltage Lateral Mos Devices in Low Vltage Cmos-Compatible Process Steps
Patent: 5,622,878 →
Application: 08/474,647 →
Digital Down Converter and Method
Patent: 5,757,794 →
Application: 08/478,682 →
Formatter
Patent: 5,633,815 →
Application: 08/478,683 →
Defect Control in Formation of Dielectrically Isolated Semiconductor Device Regions
Patent: 5,750,432 →
Application: 08/481,115 →
Local Oxidation Process for High Field Threshold Applications
Patent: 5,580,816 →
Application: 08/481,116 →
Battery Operated Inverter Circuit for Capacitive Loads Such as Electroluminescent Lamps
Patent: 5,557,175 →
Application: 08/490,016 →
Electroluminescent Lamp Driver System
Patent: 5,539,707 →
Application: 08/490,952 →
Sign Bit Integrator and Method
Patent: 5,617,473 →
Application: 08/493,454 →
Level Shifter with Improved Rejection of Voltage Variations
Patent: 5,627,489 →
Application: 08/493,824 →
Offset Adjustment for Fully Differential Amplifiers
Patent: 5,736,885 →
Application: 08/494,395 →
Digital Decoder and Method for Decoding Composite Video Signals
Patent: 5,621,477 →
Application: 08/496,868 →
Multistandard Decoder for Video Signals and Video Signal Decoding Method
Patent: 5,621,478 →
Application: 08/497,008 →
Temperature Insensitive Filter Tuning Network and Method
Patent: 5,572,161 →
Application: 08/497,045 →
Sample Rate Converter and Sample Rate Conversion Method
Patent: 5,619,270 →
Application: 08/497,181 →
Semi-Insulating Wafer
Patent: 5,773,151 →
Application: 08/497,404 →
Method of Making Non-Uniformly Nitrided Gate Oxide
Patent: 5,650,344 →
Application: 08/503,048 →
Fast Recovery Temperature Compensated Reference Source
Patent: 5,621,307 →
Application: 08/505,671 →
Automatic Fault Monitoring System and Motor Control System Incorporating Same
Patent: 5,642,247 →
Application: 08/505,695 →
Amplifier Circuit with Dynamic Output Stage Biasing
Patent: 5,568,090 →
Application: 08/506,529 →
Inverted Bjt Current Sources/Sinks in Rf Circuits and Methods
Patent: 5,654,662 →
Application: 08/506,978 →
Device and Method for Enhancing Thermal and High Frequency Performance of Integrated Circuit Packages
Patent: 5,581,444 →
Application: 08/507,192 →
Wide Common Mode Range Comparator and Method
Patent: 5,614,852 →
Application: 08/512,417 →
Integrated Circuit with Diamond Insulator
Patent: 5,650,639 →
Application: 08/513,950 →
Silicon on Insulator Process with Recovery of a Device Layer from an Etch Stop Layer
Patent: 5,985,728 →
Application: 08/522,728 →
Method of Manufacturing a Programmable Hybrid Balance Network
Patent: 5,610,093 →
Application: 08/527,548 →
Circuit Compensating for Capacitance at Inverting Input of Current Feedback Amplifier
Patent: 5,578,967 →
Application: 08/535,936 →
Device and Method for Improving Corrosion Resistance and Etch Tool Integrity in Dry Metal Etching
Patent: 5,830,279 →
Application: 08/536,257 →
Sampled Data-Biasing of Continuous Time Integrated Circuit
Patent: 5,621,355 →
Application: 08/537,051 →
Method of Making Jfet Structures for Semiconductor Devices with Complementary Bipolar Transistors
Patent: 5,652,153 →
Application: 08/543,754 →
Magnetic Boats
Patent: 5,669,599 →
Application: 08/552,711 →
Improved Discrete Programming Methodology and Circuit for an Active Transconductance-C Filter
Patent: 5,666,083 →
Application: 08/560,289 →
Monolithic Power Converter with a Power Switch as a Current Sensing Element
Patent: 5,723,974 →
Application: 08/561,304 →
Apparatus for Controlling the Reset of a Bus Connected Transceiver
Patent: 5,610,792 →
Application: 08/562,609 →
Power Control Chip with Circuitry That Isolates Switching Elements and Bond Wires for Testing
Patent: 5,793,126 →
Application: 08/564,656 →
Two Stage Current Mirror
Patent: 5,631,599 →
Application: 08/571,693 →
Silicon-Glass Bonded Wafers
Patent: 5,729,038 →
Application: 08/573,099 →
Bonded Wafer Processing
Patent: 5,728,624 →
Application: 08/573,551 →
Ultra High Gain Amplifier
Patent: 5,614,866 →
Application: 08/575,292 →
Common Mode Stabilizing Circuit and Method
Patent: 5,668,468 →
Application: 08/584,366 →
Method and Apparatus for Radiation Hardened Isolation
Patent: 5,670,413 →
Application: 08/586,556 →
Composition, and Method for Using Same, for Etching Metallic Alloys from a Substrate
Patent: 5,587,103 →
Application: 08/587,692 →
Method for Providing a Silicon and Diamond Substrate Having a Carbon to Silicon Transistion Layer and Apparatus Thereof
Patent: 5,782,975 →
Application: 08/587,953 →
Differential Interpolating Switched Capacitor Filter and Method
Patent: 5,680,072 →
Application: 08/590,940 →
Electrostatic Discharge Protection Device
Patent: 5,883,414 →
Application: 08/596,079 →
High Precision Polishing Tool
Patent: 5,681,216 →
Application: 08/597,680 →
Interpolating Digital to Analog Converter Architecture for Improved Spurious Signal Suppression
Patent: 5,798,724 →
Application: 08/601,401 →
Phase Meter and Method of Providing a Voltage Indicative of a Phase Difference
Patent: 5,831,423 →
Application: 08/608,728 →
Digitally Programmable Differential Attenuator with Tracking Common Mode Reference
Patent: 5,742,204 →
Application: 08/608,812 →
Integration of High Voltage Lateral Mos Devices in Low Voltage Cmos Architecture Using Cmos-Compatible Process Steps
Patent: 5,650,658 →
Application: 08/612,695 →
Circuit for Driving an Electroluminescent Lamp
Patent: 5,677,599 →
Application: 08/613,381 →
Carrier Buffer Having Current-Controlled Tracking Filter for Spurious Signal Suppression
Patent: 5,736,903 →
Application: 08/637,140 →
Process Forming Trench Isolation Device
Patent: 5,933,746 →
Application: 08/637,937 →
Planarization Method by Use of Particle Dispersion and Subsequent Thermal Flow
Patent: 5,837,603 →
Application: 08/643,295 →
Analog-To-Digital Converter and Output Driver
Patent: 5,659,261 →
Application: 08/645,139 →
Semiconductor Device with Doped Semiconductor and Dielectric Trench Sidewall Layers
Patent: 5,856,700 →
Application: 08/646,471 →
Integrated Circuit with an Air Bridge Having a Lid
Patent: 5,825,092 →
Application: 08/650,688 →
Pre-Bond Cavity Air Bridge
Patent: 5,949,144 →
Application: 08/650,762 →
Method and Circuit for Preventing Forward Bias of a Parasitic Diode in an Integrated Circuit
Patent: 5,675,281 →
Application: 08/652,933 →
Semiconductor Packaging Apparatus
Patent: 5,965,933 →
Application: 08/654,316 →
Process for Forming a Self-Aligned Raised Source/Drain Mos Device and Device Therefrom
Patent: 5,804,846 →
Application: 08/654,393 →
Bridge Control Circuit and Method
Patent: 5,870,266 →
Application: 08/656,987 →
Integrated Circuit Air Bridge Structures and Methods of Fabricating Same
Patent: 6,492,705 →
Application: 08/658,010 →
Radiation Hardened Dielectric for Eeprom
Patent: 5,808,353 →
Application: 08/666,258 →
Clock-Controlled Precision Monostable Circuit
Patent: 5,920,219 →
Application: 08/669,066 →
Up-Conversion Mechanism Employing Side Libe-Selective Pre- Distortion Felter and Frequency Repleca-Selecting Bandpass Filter Respectively Enstalled Upstream and Downstream of Digital- to-Analog Converter
Patent: 5,930,301 →
Application: 08/671,025 →
Double Diffused Mos Device and Method
Patent: 5,817,564 →
Application: 08/671,157 →
Integrated Circuit Containing Devices Dielectrically Isolated and Junction Isolated from a Substrate
Patent: 5,841,169 →
Application: 08/671,243 →
Charge-Based Frequency Locked Loop and Method
Patent: 5,841,324 →
Application: 08/671,781 →
High Voltage Protection Circuits
Patent: 5,663,860 →
Application: 08/673,396 →
Method of Making High Voltage, Junction Isolation Semiconductor Device Having Dual Conductivity Type Buried Regions
Patent: 5,837,553 →
Application: 08/683,599 →
Electrically Variable R/C Network and Method
Patent: 5,767,757 →
Application: 08/687,995 →
Lid Wafer Bond Packaging and Micromachining
Patent: 5,798,557 →
Application: 08/705,536 →
Differential Amplifier with Improved Voltage Gain
Patent: 5,812,026 →
Application: 08/705,596 →
P-Collector H.V. Pmos Switch Vt Adjusted Source/Drain
Patent: 5,770,880 →
Application: 08/707,271 →
Two Trim Current Source and Method for a Digital-to-Analog Converter
Patent: 5,923,209 →
Application: 08/707,380 →
Bonded Wafer
Patent: 5,744,852 →
Application: 08/710,694 →
Integrated Circuit Analog-to-Digital Converter and Associated Calibration Method and Apparatus
Patent: 5,771,012 →
Application: 08/712,027 →
Digital- to- Analog Converter Having Enhanced Current Steering and Associated Method
Patent: 5,790,060 →
Application: 08/714,019 →
Wide Common Mode Range Comparator and Method
Patent: 5,789,949 →
Application: 08/719,873 →
Gas Agitated Liquid Etcher
Patent: 5,846,374 →
Application: 08/724,848 →
Surface Mount Die by Handle Replacement
Patent: 5,807,783 →
Application: 08/726,659 →
Analog-To-Digital Converter and Method of Fabrication
Patent: 5,994,755 →
Application: 08/739,898 →
Capacitor Structure in a Bonded Wafer and Method of Fabrication
Patent: 5,841,182 →
Application: 08/741,639 →
Late Process Method and Apparatus for Trench Isolation
Patent: 5,920,108 →
Application: 08/745,104 →
Driver Circuit Providing Controllable Battery Overload Protection
Patent: 5,744,984 →
Application: 08/748,641 →
Method for Cleaning Semiconductor Wafers to Improve Dice to Substrate Solderability
Patent: 5,833,758 →
Application: 08/754,596 →
Plsma Cleaning Method for Improved Ink Brand Permanency on Ic Packages
Patent: 5,882,423 →
Application: 08/754,597 →
Deep Trench Etch on Bonded Silicon Wafer
Patent: 5,914,280 →
Application: 08/771,944 →
Process for Doping Two Levels of a Double Poly Bipolar Transistor After Formation of Second Poly Layer
Patent: 5,776,814 →
Application: 08/775,360 →
Complementary Mutliplexer with Low Disabled-Output Capacitance, and Method
Patent: 5,923,207 →
Application: 08/777,101 →
Re-Sampling Circuit and Modulator Using Same
Patent: 5,764,113 →
Application: 08/781,334 →
Interpolator Using a Plurality of Polynomial Equations and Associated Methods
Patent: 5,949,695 →
Application: 08/781,736 →
Bonded Wafer Processing
Patent: 5,780,311 →
Application: 08/783,792 →
High Frequency Analog Transistors, Method of Fabrication and Circuit Implementation
Patent: 5,892,264 →
Application: 08/786,569 →
Pivot Sample Block Cross-Section Tool
Patent: 5,830,048 →
Application: 08/798,039 →
Integrated Circuit with Thin Film Resistors and a Method for Co-Patterning Thin Film Resistors with Different Compositions
Patent: 5,976,944 →
Application: 08/799,793 →
Dc-To-Dc Converter Having Enhanced Control Features and Associated Methods
Patent: 5,793,193 →
Application: 08/799,959 →
Dc-To-Dc Converter Having Fast Over-Current Detection and Associated Methods
Patent: 5,821,740 →
Application: 08/800,420 →
Dc-To-Dc Converter Having Charge Pump and Associated Methods
Patent: 5,808,883 →
Application: 08/800,421 →
Video Sync Signal Slicing Using Variable Gain Control
Patent: 5,867,222 →
Application: 08/803,777 →
Ohmic Contact to Lightly Doped Islands from a Conductive Rapid Diffusion Buried Layer
Patent: 5,895,953 →
Application: 08/810,127 →
Polysilicon Filled Trench Isolation Structure for Soi Integrated Circuits
Patent: 6,096,621 →
Application: 08/841,493 →
A Method for Making a Contact Structure for a Polysilicon Filled Trench Isolation
Patent: 6,037,239 →
Application: 08/841,494 →
Bonded Wafer Processing
Patent: 5,801,084 →
Application: 08/843,302 →
Method of Forming Retrograde Well in Bonded Waffers
Patent: 6,140,205 →
Application: 08/844,973 →
Contact Regions for Narrow Trenches in Semiconductor Devices and Method
Patent: 5,962,908 →
Application: 08/845,214 →
Reduced Output Capacitance Circuit for Driving a Grounded Load in Response to a Stepped Input
Patent: 5,898,334 →
Application: 08/854,376 →
Constant Amplitude Vs. Frequency Oscillator
Patent: 5,874,865 →
Application: 08/854,517 →
Circuit and Method for Synchronizing Outputs of Two Simultaneously Transmitting Devices in a Multiplexed Communication System
Patent: 6,108,352 →
Application: 08/854,681 →
Reduce Width, Differentially Doped Vertical Jfet Device
Patent: 5,945,699 →
Application: 08/855,385 →
Integrated Circuit Chip Structure for Improved Packaging
Patent: 5,900,643 →
Application: 08/858,845 →
Level Shifter Stage with Punch Through Diode
Patent: 5,929,502 →
Application: 08/868,813 →
Punch-Through Diodes and Applications
Patent: 5,929,503 →
Application: 08/868,815 →
Temperature Insensitive Bandgap Voltage Generator Tracking Power Supply Variations
Patent: 5,856,742 →
Application: 08/873,902 →
Dynamic Regulator for a Dc-to-Dc Power Converter and Related Methods
Patent: 5,926,384 →
Application: 08/883,624 →
Non-Uniformly Nitrided Gate Oxide and Method
Patent: 5,808,348 →
Application: 08/884,032 →
Low Voltage Rf Amplifier and Mixed with Single Bias Block and Method
Patent: 6,018,270 →
Application: 08/884,635 →
Method and Apparatus for Calibrating Integrated Circuit Analog-to-Digital Converters
Patent: 5,861,826 →
Application: 08/885,273 →
Processor Controlled Analog-to-Digital Converter Circuit
Patent: 5,892,472 →
Application: 08/885,274 →
Method for Forming Complementary Wells and Self-Aligned Trench with a Single Mask
Patent: 5,956,583 →
Application: 08/885,707 →
Multilayer Microtip Probe and Method
Patent: 5,892,223 →
Application: 08/885,897 →
Hermetic Thin Oack Semiconductor Device
Patent: 6,157,076 →
Application: 08/885,923 →
Digital-To-Analog Converter Including Current Cell Matrix with Enhanced Linearity and Associated Methods
Patent: 5,949,362 →
Application: 08/916,569 →
Comparator with Small Signal Suppression Circuitry
Patent: 5,892,375 →
Application: 08/918,345 →
Constant Slew Rate Amplifier
Patent: 6,040,707 →
Application: 08/929,734 →
Knock Sensor System for Detecting and Responding to a Disconnect Condition
Patent: 5,942,677 →
Application: 08/931,340 →
Method Fo Fabricating Bicmos Devices
Patent: 5,851,864 →
Application: 08/956,074 →
Inverted Thin Film Resistor
Patent: 6,034,411 →
Application: 08/960,337 →
Schmitt Trigger-Configured Esd Protection Circuit
Patent: 5,978,192 →
Application: 08/964,672 →
Negative Biasing of Isolation Trench Fill to Attract Mobile Positive Ions Away from Bipolar Device Regions
Patent: 6,051,474 →
Application: 08/968,618 →
Low Distortion Current Feedback Amplifier with Dynamic Biasing
Patent: 5,977,829 →
Application: 08/972,887 →
Monolithic Class D Amplifier
Patent: 5,973,368 →
Application: 08/973,769 →
Multiple Output Dc-to-Dc Converter Having Enhanced Noise Margin and Related Methods
Patent: 6,058,030 →
Application: 08/974,862 →
Network for Improving Electro-Magnetice Interference Response
Patent: 5,920,224 →
Application: 09/024,203 →
Devices with Patterned Wells and Method for Forming Same
Patent: 6,555,894 →
Application: 09/062,964 →
Publication: US 2002/0158312
Lid Wafer Bond Packaging and Micromachining
Patent: 5,915,168 →
Application: 09/073,776 →
Decapsulating Method and Apparatus for Integrated Circuit Packages
Patent: 6,054,012 →
Application: 09/106,622 →
Method of Creating a Solderable Metal Layer on Glass or Ceramic
Patent: 6,159,663 →
Application: 09/107,475 →
Linear Voltage Regulator Compatible with Bipolar and Mosfet Pass Devices and Associated Methods
Patent: 6,005,303 →
Application: 09/108,059 →
Electrostatic Discharge Locating Apparatus and Method
Patent: 6,064,340 →
Application: 09/108,963 →
Flat Power Rack
Patent: 6,057,612 →
Application: 09/109,268 →
Surface Mount Die by Handle Replacement
Patent: 6,114,768 →
Application: 09/110,721 →
Parasitic Current Barriers
Patent: 6,278,186 →
Application: 09/139,932 →
Programmable Subscriber Loop Interface Circuit and Method
Patent: 6,665,398 →
Application: 09/145,182 →
Analog-To-Digital Converter Having Enhanced Accuracy Gain Stage, and Associated Devices and Methods
Patent: 6,107,950 →
Application: 09/148,955 →
Digital-To-Analog Converter Including Current Sources Operable in a Predetermined Sequence and Associated Methods
Patent: 6,118,398 →
Application: 09/149,154 →
Device Containing Sample Preparation Sites for Transmission Electron Microscopic Analysis and Processes of Formation and Use
Patent: 6,140,652 →
Application: 09/150,429 →
Differential Amplifier with Improved Voltage Gain Using Operational Amplifiers to Eliminate Diode Voltage Drops
Patent: 6,031,424 →
Application: 09/150,788 →
Load Current Control Circuitry for Power Supplies Driving a Common Load for Providing a Uniform Temperature Distribution
Patent: 6,204,720 →
Application: 09/169,512 →
Integrated Circuit Air Bridge Structures and Methods of Fabricating Same
Patent: 6,211,056 →
Application: 09/199,292 →
Semiconductor Packaging Method
Patent: 6,114,191 →
Application: 09/204,904 →
Apparatus and Method for Testing Subscriber Loop Interface Circuits
Patent: 6,519,322 →
Application: 09/208,457 →
Dc-To-Dc Converter with Inductor Current Sensing and Related Methods
Patent: 5,982,160 →
Application: 09/220,780 →
Complementary Multiplexer with Low Disabled-Output Capacitance, and Method
Patent: 6,114,896 →
Application: 09/247,510 →
Method for Forming a Bonded Substrate Containing a Planar Intrinsic Gettering Zone and Substrate Formed by Said Method
Patent: 6,255,195 →
Application: 09/255,231 →
Method for Fabricating Electrostatic Discharge Protection Device
Patent: 6,051,457 →
Application: 09/268,605 →
Wafer Trench Article and Process
Patent: 6,365,953 →
Application: 09/283,530 →
Publication: US 2001/0045614
Bonded Wafer with Metal Silicidation
Patent: 6,909,146 →
Application: 09/316,580 →
Defect Gettering by Induced Stress
Patent: 6,274,460 →
Application: 09/334,987 →
Current-Controlled Carrier Tracking Filter for Improved Spuriou Signal Suppression
Patent: 6,233,293 →
Application: 09/334,998 →
Brushless Multipass Silicon Wafer Cleaning Process for Post Chemical Mechanical Polishing Using Immersion
Patent: 6,526,995 →
Application: 09/342,948 →
Method of Manufacturing a Plated Electronic Termination
Patent: 7,174,626 →
Application: 09/343,845 →
Publication: US 2002/0029473
Low Temperature Coefficient Resistor (Tcrl)
Patent: 6,351,021 →
Application: 09/345,929 →
Reduced Substrate Capcitance High Performance Soi Process
Patent: 6,403,447 →
Application: 09/348,782 →
Circuit Providing a Negative Resistance to Offset Error Voltage for Use with a Folded Cascode Amplifier
Patent: 6,229,394 →
Application: 09/398,261 →
Alternative Video Sync Detector
Patent: 6,573,943 →
Application: 09/398,375 →
High performance intermediate stage circuit for a rail-to-rail input/output CMOS operational amplifier
Patent: 6,300,834 →
Application: 09/735,216 →
High Speed, Low-Power Cmos Circuit with Constant Output Swing and Variable Time Delay for a Voltage Controlled Oscillator
Patent: 6,501,317 →
Application: 09/828,398 →
Publication: US 2002/0145460
Distortion Improvement in Amplifiers
Patent: 6,448,853 →
Application: 09/829,326 →
High Performance Intermediate Stage Circuit for a Rail-to-Rail Input/Output Cmos Operational Amplifier
Patent: 6,384,683 →
Application: 09/884,712 →
Related Assignments (5)
Other recorded transfers of the patents in this record — the chain of ownership.
Change of Name Apr 14, 2006
From: INTERSIL CORPORATION
To: INTERSIL COMMUNICATIONS, INC.
Reel/Frame 017468/0602 →
Assignment of Assignor's Interest Apr 14, 2006
From: INTERSIL COMMUNICATIONS, INC.
To: INTERSIL AMERICAS, INC.
Reel/Frame 017468/0607 →
Security Agreement May 4, 2010
From: INTERSIL CORPORATION; TECHWELL, INC.; INTERSIL COMMUNICATIONS, INC.; QUELLAN, INC.
To: MORGAN STANLEY & CO. INCORPORATED
Reel/Frame 024329/0411 →
Security Agreement May 5, 2010
From: INTERSIL CORPORATION; TECHWELL, INC.; INTERSIL COMMUNICATIONS, INC.; QUELLAN, INC.
To: MORGAN STANLEY & CO. INCORPORATED
Reel/Frame 024329/0831 →
Security Agreement May 5, 2010
From: INTERSIL CORPORATION; TECHWELL, INC.; INTERSIL COMMUNICATIONS, INC.; QUELLAN, INC.
To: MORGAN STANLEY & CO. INCORPORATED
Reel/Frame 024390/0608 →