Method for fabricating a semiconductor storage device having an increased dielectric film area
View Patent ↗A semiconductor device of the present invention is a semiconductor memory having a charge storage film. Recesses or holes which effectively increase the capacitance of a floating gate or a memory cell capacitor are formed in the charge storage film. These recesses or holes are formed at the same time the floating gate electrode or the lower electrode of the capacitor is isolated into the form of islands. A dielectric film and a polysilicon film is formed on the isolated island floating gate electrodes or lower electrodes. These recesses or holes increase the surface area of the dielectric film and improve the write and erase characteristics of a memory cell.
1. A method of fabricating a semiconductor device, comprising:
the first step of defining an element active region by forming an element isolation structure on a semiconductor substrate;
the second step of forming an insulating film on said semiconductor substrate in said element active region;
the third step of forming a first conductive film on an entire surface of said semiconductor substrate including said insulating film, and said element isolation structure;
the fourth step of forming a mask pattern having first and second openings on said first conductive film;
the fifth step etching said first conductive film until said element isolation structure is exposed in said first opening by using said mask pattern as a mask, thereby dividing said first conductive film, and simultaneously forming a recess in said second opening where said first conductive film forms a bottom of said recess;
the sixth step of forming a dielectric film so as to cover a surface of said firs conductive film; and
the seventh step of forming a second conductive film on said dielectric film opposing said first conductive film through said dielectric film.
2. A method according to claim 1 , further comprising, after the seventh step, the eighth step of doping an impurity into said semiconductor substrate in said element active region to form a pair of impurity diffusion layers in surface regions of said semiconductor substrate on two sides of said first conductive film.
3. A method according to claim 1 , wherein in the fourth step, said mask pattern is so formed that a width of said first opening is not less than twice a width of said second opening.
4. A method according to claim 1 , further comprising, between the third and fourth steps, the ninth step of planarizing said first conductive film by polishing, and
wherein in the fourth step, said mask pattern is so formed that said second opening is positioned above said element active region.
5. A method of fabricating a semiconductor device, comprising:
the first step of forming a first conductive film in an insulating film region on a semiconductor substrate;
the second step of forming a mask pattern having first and second openings of different dimensions on said first conductive film;
the third step of etching said first conductive film by using said mask pattern as a mask, thereby dividing said first conductive film conforming to a shape of said first opening so as to reach said insulating film region, and simultaneously forming a cylindrical hole below said second opening in which a surface of said insulating film region is exposed in a surface of said divided first conductive film conforming to a shape of the other opening;
the fourth step of forming an insulating film so as to cover a surface of said first conductive film; and
the fifth step of forming a second conductive film so as to cover a surface of said insulating film opposing said first conductive film through said insulating film.
6. A method according to claim 5 , wherein in the third step, said recess is so formed as to reach said insulating film region, thereby forming a hole in which a surface of said insulating film region is exposed.
7. A method of fabricating a semiconductor device, comprising:
the first step of defining an element active region by forming an element isolation structure on a semiconductor substrate;
the second step of forming an insulating film on said semiconductor substrate in said element active region;
the third step of forming a first conductive film on an entire surface including said insulating film and said element isolation structure;
the fourth step of forming a mask pattern having at least first and second openings on said first conductive film;
the fifth step of etching said first conductive film until said element isolation structure is exposed in said first and second openings by using said mask pattern as a mask, thereby dividing said first conductive film below said first opening, and simultaneously forming a cylindrical hole extending through said first conductive film below said second opening and said first conductive film is etched until said insulating layer is exposed in said first opening;
the sixth step of forming a dielectric film so as to cover said first conductive film; and
the seventh step of forming a second conductive film on said dielectric film and opposing said first conductive film through said dielectric film.
8. A method according to claim 7 , further comprising, after the seventh step, the eight step of doping an impurity into said semiconductor substrate in said element active region to form a pair of impurity diffusion layers in surface regions of said semiconductor substrate on two sides of said first conductive film.
9. A method according to claim 7 , further comprising, between the third and fourth steps, the ninth step of planarizing said first conductive film by polishing.
10. A method according to claim 7 , wherein in the first step, a field shield element isolation structure in which a shield plate electrode is embedded is formed on said semiconductor substrate.
11. A method of fabricating a semiconductor substrate, comprising:
the first step of defining an element active region by forming an element isolation structure on a semiconductor substrate;
the second step of forming a gate oxide film and a gate electrode on said semiconductor substrate in said element active region;
the third step of doping an impurity into said semiconductor substrate in said element active region to form a pair of impurity diffusion layers in surface regions of said semiconductor substrate on two sides of said gate electrode;
the fourth stop of forming an insulating interlayer on an entire surface of said semiconductor substrate;
the fifth step of forming a hole in said insulating interlayer in which one of said impurity diffusion layers is exposed;
the sixth step of forming a first conductive film on said insulating interlayer which fills said hole electrically connected to one of said impurity diffusion layers;
the seventh step of forming a mask pattern having at least first and second openings on said first conductive film;
the eighth step of etching said first conductive film by using said mask pattern as a mask, thereby dividing said first conductive film below said first opening, and simultaneously forming a cylindrical hole extending through said first conductive film below said second opening, said first conductive film is etched until said insulating interlayer is exposed in said first opening;
the ninth step of forming a dielectric film so as to cover a surface of said first conductive film; and
the tenth step of forming a second conductive film so as to cover said dielectric film opposing said first conductive film through said dielectric film.
12. A method according to claim 11 , further comprising, between the sixth and seventh steps of planarizing said first conductive film by polishing.
13. A method according to claim 11 , wherein in the first step, a field shield element isolation structure in which a shield plate electrode is embedded is formed on said semiconductor substrate.