Method of making a memory cell with polished insulator layer
View Patent ↗An improved method of making a flash memory cell including a substrate having a floating gate of a first thickness includes depositing an insulator on the substrate and over the floating gate. The insulator is preferably a high quality oxide. A portion of the insulator not covering the floating gate has a second thickness which is greater than the first thickness of the floating gate. The method further includes polishing the insulator until the second thickness is substantially equal to the first thickness. Polishing results in a planar floating gate and insulator layer. The method further includes sequentially depositing a dielectric layer and a control gate layer on the planar floating gate and insulator layer and then etching these layers to complete the stacked gate structure of the memory cell.
1. A method of making a flash memory cell including a substrate and a tunnel oxide layer formed on the substrate and a floating gate, the method comprising:
depositing an insulator layer comprising a high temperature oxide directly on exposed portions of the tunnel oxide layer and the floating gate, the insulator layer being deposited to a thickness greater than a thickness of the floating gate, wherein the insulator layer is in contact with vertical surfaces of the floating gate to prevent charge leaking from the floating gate, and wherein the insulator layer is formed by a LPCVD process;
polishing the insulator layer immediately after the step of depositing the insulator layer to reduce the thickness of the insulator layer and to provide a planar surface that exposes a top surface of the floating gate and the insulator layer; and
depositing an ONO layer on the planar surface directly over the exposed top surface of the floating gate and the insulator layer.
2. The method of claim 1 , wherein polishing the insulator layer includes using chemical mechanical polishing.
3. The method of claim 1 , further comprising:
depositing a control gate layer on the ONO layer; and
etching the control gate layer and the ONO layer to form a stacked gate structure of the flash memory cell.
4. A method of making a flash memory cell having a substrate and a tunnel oxide layer formed on the substrate, the method comprising:
depositing a floating gate layer on the tunnel oxide layer to a first thickness;
etching the floating gate layer, to provide a floating gate;
depositing an insulator layer comprising a high temperature oxide directly on exposed portions of the tunnel oxide layer and the floating gate, wherein the insulator layer has a second thickness that is greater than the first thickness, wherein the insulator layer is in contact with vertical surfaces of the floating gate, and wherein the insulator layer is formed by a LPCVD process;
polishing the insulator layer immediately after the step of depositing the insulator layer to provide a planar surface that exposes a top surface of the floating gate and the insulator layer; and
depositing an ONO layer on the planar surface directly over the exposed top surface of the floating gate and the insulator layer.
5. The method of claim 4 , wherein the first thickness of the floating gate layer is between approximately 500 Å and 2000 Å, and the second thickness of the insulator layer, is between approximately 1000 Å and 5000 Å.
6. The method of claim 4 , wherein polishing the insulator layer includes using chemical mechanical polishing.
7. The method of claim 4 , further comprising:
depositing a control gate layer on the ONO layer; and
etching the control gate layer and the ONO layer to form a stacked gate structure of the flash memory cell.
8. The method of claim 4 , wherein the floating gate layer comprises doped polysilicon.
9. The method of claim 4 , wherein the floating gate layer comprises doped amorphous silicon.
10. A method of making a flash memory cell including a substrate, a tunnel oxide layer formed on the substrate and a floating gate, the method comprising:
depositing an insulator layer comprising a high quality oxide directly on the tunnel oxide layer and the floating gate, wherein the insulator layer is deposited to a thickness greater than a thickness of the floating gate, wherein the insulator layer is formed on and in contact with vertical surfaces of the floating gate to prevent charge leaking from the floating gate, and wherein the high quality oxide is formed by a LPCVD process;
polishing the insulator layer immediately after the step of depositing the insulator layer to reduce the thickness of the insulator layer and to provide a planar surface that exposes a top surface of the floating gate and the insulator layer; and
depositing an ONO layer on the planar surface over the exposed top surface of the floating gate and the insulator layer.