Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program
View Patent ↗A semiconductor device has multilevel memory cells, each cell storing at least three levels of data each. At least a first data composed of first data bits and a second data composed of second data bits are arranged in order that at least a bit of an N-order of the first bits and a bit of the N-order of the second bits are stored in one of the cells, the N being an integral number. A voltage corresponding to the N-order bits is generated and applied to the one of the cells in response to an address information corresponding thereto. Another semiconductor device has multilevel memory cells arranged so as to correspond to a physical address space, each cell storing 2 n levels of data each expressed by n (n≧2) number of bits (X 1 , X 2 , . . . , Xn). A logical address is converted into a physical address of the physical address space. Judging is made whether a logical address space including the logical address matches the physical address space. When matched, the most significant bit X 1 is specified once using a reference value. The specified bit is output from one of the cells corresponding to the physical address. If not matched, the bits (X 2 , . . . , Xn) are specified by n—time specifying operation maximum using maximum n number of different reference values. The data writing/reading operations to/from the semiconductor devices can be stored in a computer readable medium as program codes for causing a computer to execute these operations.
1. A computer readable medium storing program code for causing a computer to write data of bits in a semiconductor device having a plurality of multilevel memory cells, each cell storing at least three levels of data each, comprising:
first program code means for entering at least a first data composed of a plurality of first data bits and a second data composed of a plurality of second data bits, the first and the second data having been coded by a coding method; and
second program code means for arranging the first and the second data bits to store at least a bit of an N-order of the first data bits and at least a bit of an M-order of the second data bits in one of the cells, the N and M being different integral numbers.
2. The computer readable medium according to claim 1 further comprising:
third program code means for initiating generation of voltages corresponding to the N- and M-order bits; and
fourth program code means for applying the voltage to the one of the cells in response to an address information corresponding to the one of the cells.
3. A semiconductor device having a plurality of multilevel memory cells, each cell storing one of at least three levels of data each, the semiconductor device comprising:
a controller for entering at least a first data composed of a plurality of first data bits and a second data composed of a plurality of second data bits, the first and second data having been coded by a coding method; and
a bit data separator for separating the first and second data bits to store at least a bit of an N-order of the first data bits and at least a bit of an M-order of the second data bits in one of the cells, the N and M being different integral numbers.
4. The semiconductor device according to claim 3 , wherein the bit data separator controls the number of bits to be stored in at least one of the cells in accordance with capability of code error correction of the coding method.
5. The semiconductor device according to claim 3 , wherein the bit data separator puts the bits of O number of code data, each code data having a code length P, into positions of arrangement in O lines×P rows and stores the O number of bits in each cell, the O and P being an integral number.
6. The semiconductor device according to claim 3 , wherein the multilevel memory cells are non-volatile semiconductor memories.
7. A method of writing at least one code data coded by a coding method in a semiconductor device having a plurality of multilevel memory cells, each cell storing one of at least three levels of data each, the method comprising the steps of:
entering at least a first data composed of a plurality of first data bits and a second data composed of a plurality of second data bits, the first and second data having been coded by a coding method; and
separating the first and second data bits to store at least a bit of an N-order of the first data bits and at least a bit of an M-order of the second data bits in one of the cells the N and M being different integral numbers.