Pipelined processing with commit speculation staging buffer and load/store centric exception handling
View Patent ↗A load/store centric exception handling system provided in accordance with the principles of this invention that provides a more efficient processor exception handling system wherein a speculative commit control signal (SpecComId) is generated whenever a load or store instructions is detected by the pipeline issuing unit (PIU). This speculative commit signal is sent to a Load Store Unit (LSU) which combines the SpecComID with the completed instructions in its pipeline to generate an actual commit signal (ComId) that is coupled to other processor units. Depending on what type of instructions are in the pipeline, SpecComID can be generated as early as Q stage or as late as C stage. LSU or Exc Free instructions can be speculatively committed in Q stage to move the speculative commit point up in processor pipeline. Exc Taking instructions speculatively commit in the C stage to move the speculative commit point down pipeline.
1. A load/store centric exception processing method in a microprocessor employed in executing a plurality of instructions as part of a computing system comprising the steps of:
issuing the plurality of instructions at a first pipeline state, the plurality of instructions including a plurality of exception free instructions and a plurality of exception taking instructions;
completing each of the plurality of instructions;
committing speculatively each of the plurality of instructions at a second pipeline stage when any of a first plurality of conditions is true such that only the plurality of exception free instructions are committed speculatively:
generating an actual commit (ComId) for each of the plurality of exception free instructions selected by the committing speculatively, each ComId including a commit speculation control signal (SpecComId) and one of the plurality of identification for one of the plurality of exception free instructions;
retiring the plurality of exception free instructions at a third pipeline stage when any of a second plurality of conditions is true;
taking the plurality of exception taking instructions at the third pipeline stage; and
retiring the plurality of exception taking instructions at the third pipeline stage.
2. The method of claim 1 wherein the first plurality of conditions comprises:
for each of the plurality of instructions, the instruction is an exception free instruction;
for each of the plurality of instructions, the instruction is a Load/Store Unit (LSU) instruction; and
for each of the plurality of instructions, the instruction is a done without exceptions instruction.
3. The method of claim 1 wherein the second plurality of conditions comprises:
for each of the plurality of exception free instructions, all older instructions have been retired; and
for each of the plurality of exception free instructions, the exception free instruction is done.
4. The method of claim 3 wherein the issuing the plurality of instructions further includes:
writing the plurality of instructions into an instruction staging buffer; and
tagging each of the plurality of instructions with a write pointer.
5. The method of claim 4 wherein the completing each of the plurality of instructions further includes:
writing to the instruction staging buffer that one of the plurality of instructions is complete; and
reporting, if any, an exception corresponding to the one of the plurality of instructions.
6. The method of claim 1 wherein the first pipeline stage is a Q stage.
7. The method of claim 1 wherein the second pipeline stage is selected from the group consisting of: a Q stage, an E stage, a D stage and a C stage.
8. The method of claim 1 wherein the third pipeline stage is a W stage.
9. The method of claim 1 wherein the SpecComId is generated by a Pipeline & Issuing Unit (PIU).
10. The method of claim 1 wherein the ComId is generated by the LSU.