Patent Assignment
Reel/Frame 023926/0338
Assignment of Assignor's Interest
Recorded: 2010-02-11
Pages: 25
Assignor
RMI CORPORATION
Executed: 2009-12-29
Assignee
NETLOGIC MICROSYSTEMS, INC.
1875 CHARLESTON ROAD, MOUNTAIN VIEW, CALIFORNIA, 94043
Covered Properties
(141)
Scheduling Techniques for Data Cells in a Data Switch
Patent:
6,229,812 →
Application:
08/872,530 →
Method and Apparatus for Dual Issue of Program Instructions to Symmetric Multifunctional Execution Units
Patent:
6,035,388 →
Application:
08/883,147 →
A Writeback Cache Cell with a Dual Ported Dirty Bit Cell and Method for Operating Such a Cache Cell
Patent:
6,055,606 →
Application:
08/924,604 →
Asynchronous Transfer Mode Switching Architectures Having Connection Buffers
Patent:
6,069,893 →
Application:
08/959,056 →
Cache Memory Cell with a Pre-Programmed State
Patent:
6,070,229 →
Application:
08/982,822 →
Method and Apparatus for Communicating Signals Between Circuits Operating at Different Frequencies
Patent:
6,092,129 →
Application:
09/059,614 →
System Bus Arbitrator for Facilitating Multiple Transactions in a Computer System
Patent:
6,085,271 →
Application:
09/059,615 →
Asynchronous Transfer Mode Traffic Shapers
Patent:
6,198,723 →
Application:
09/060,228 →
Method and Apparatus for Forming a Virtual Circuit
Patent:
6,349,098 →
Application:
09/062,301 →
Circuit, Architecture and Method for Analyzing the Operation of a Digital Processing System
Patent:
6,311,292 →
Application:
09/126,680 →
Floating-Point and Integer Multiply-Add and Multiply-Accumulate
Patent:
6,480,872 →
Application:
09/235,148 →
Apparatus and Method for Operating a Dual Port Memory Cell
Patent:
6,252,818 →
Application:
09/277,659 →
Processor with Multiple Execution Units and Local and Global Register Bypasses
Patent:
6,088,784 →
Application:
09/281,620 →
Method and Apparatus for Vector Register with Scalar Values
Patent:
6,530,011 →
Application:
09/422,045 →
Method and Apparatus for Dual Issue of Program Instructions to Symmetric Multifunctional Execution Units
Low-voltage CMOS phase-locked loop (PLL) for high-performance microprocessor clock generation
Patent:
6,292,061 →
Application:
09/562,055 →
Floating Point Pipeline Method and Circuit for Fast Inverse Square Root Calculations
Patent:
6,963,895 →
Application:
09/562,056 →
Digital programmable delay element
Patent:
6,255,879 →
Application:
09/562,057 →
Reduced line select decoder for a memory array
Patent:
6,252,819 →
Application:
09/562,058 →
Method and System for Reducing Taken Branch Penalty
Patent:
6,735,689 →
Application:
09/562,061 →
Scalable Replacement Method and System in a Cache Memory
Patent:
6,694,408 →
Application:
09/562,062 →
Dynamic circuit using exclusive states
Application:
09/562,063 →
Low-Power Cache System and Method
Patent:
7,487,369 →
Application:
09/562,071 →
Pipelined Processing with Commit Speculation Staging Buffer and Load/Store Centric Exception Handling
Patent:
7,188,232 →
Application:
09/564,715 →
Cache Memory Cell with a Pre-Programmed State
Patent:
6,400,599 →
Application:
09/569,543 →
Single Phase Edge Trigger Register
Patent:
6,388,471 →
Application:
09/569,818 →
A High Performance Method and System for Processing Informantion on an Integrated Circuit
Patent:
6,775,788 →
Application:
09/654,717 →
Method for Coordinating Information Flow Between Components
Patent:
7,062,767 →
Application:
09/654,718 →
Method and System for Initiating Computation Upopn Unordered Receipt of Data
Patent:
6,708,282 →
Application:
09/654,759 →
Asynchronous Transfer Mode Traffic Shapers
Scheduling Techniques for Data Cells in a Data Switch
System and Method for a High Speed, Bi-Directional, Zero Turnaround Time, Pseudo Differential Bus Capable of Supporting Arbitrary Number of Drivers and Receivers
Patent:
6,686,774 →
Application:
09/909,316 →
Network Switch with a Parallel Shared Memory
Programmable Integrated Circuit for Use in a Network Switch
Network Switch for Routing Network Traffic
Dynamic circuit using exclusive states
Application:
09/970,250 →
Dynamic Circuit Using Exclusive States
Patent:
7,028,069 →
Application:
09/996,865 →
Adaptive Link Quality Management for Wireless Medium
Network node with multi-medium interfaces
Application:
10/023,633 →
Publication:
US 2002/0075868
Method of Generating, Transmitting, Receiving and Recovering Synchronous Frames with Non-Standard Speeds
Hybrid Network to Carry Synchronous and Asynchronous Traffic Over Symmetric and Asymmetric Links
Integration of network, data link, and physical layer to adapt network traffic
Application:
10/023,972 →
Publication:
US 2002/0075869
Dynamic Mixing Tdm Data with Data Packets
Interfacing 622.08 Mhz Line Interface to a 77.76 Mhz Sonet Framer
Patent:
7,206,323 →
Application:
10/093,324 →
Advanced Error Correcting Optical Transport Network
Patent:
7,099,584 →
Application:
10/209,079 →
Advanced Multi-Protocol Optical Transport Network
Patent:
7,164,860 →
Application:
10/210,750 →
Advanced Telecommunications Router and Crossbar Switch Controller
Advanced Communication Apparatus and Method for Verified Communication
Patent:
7,536,631 →
Application:
10/452,229 →
Multi-Protocol Communication Circuit
Patent:
8,149,862 →
Application:
10/452,563 →
Advanced telecommunications processor
Application:
10/682,579 →
Publication:
US 2004/0103248
Encoding-Based Multicast Packet Duplication Control Suitable for Vlan Systems
Method and Apparatus for Providing Internal Table Extensibility with External Interface
Method and Apparatus for Packet Transmit Queue Control
Method and Apparatus for Providing Internal Table Extensibility Based on Product Configuration
Method and Apparatus for Enhanced Hashing
Method and Apparatus for Implementing a Search Engine Using an Sram
Patent:
7,234,019 →
Application:
10/735,107 →
Technique for Deallocation of Memory in a Multicasting Environment
Patent:
7,260,095 →
Application:
10/739,874 →
Method and Device for the Classification and Redirection of Data Packets in a Heterogeneous Network
Method and Apparatus for Determining Precedence in a Classification Engine
Patent:
7,213,111 →
Application:
10/789,667 →
Method and Apparatus for Constructing a Search Key
Patent:
7,426,608 →
Application:
10/789,668 →
Method and Apparatus for Action Group Generation and Arbitration in a Classification Engine
Patent:
7,516,119 →
Application:
10/789,791 →
Stacked Network Switch Using Resilient Packet Ring Communication Protocol
Patent:
7,613,201 →
Application:
10/826,215 →
Advanced Processor System Using Request, Data, Snoop, and Response Rings
Advanced Processor with Cache Coherency
Advanced Processor Scheduling in a Multithreaded System
Advanced Processor with System on a Chip Interconnect Technology
Advanced Processor Translation Lookaside Buffer Management in a Multithreaded System
Advanced processor with a thread aware return address stack optimally used across active threads
Application:
10/930,175 →
Publication:
US 2005/0033831
Advanced Processor with Use of Bridges on a Data Movement Ring for Optimal Redirection of Memory and I/O Traffic
Advanced Processor with Scheme for Optimal Packet Flow in a Multi-Processor System on a Chip
Advanced Processor with Implementation of Memory Ordering on a Ring Based Data Movement Network
Advanced Processor with Mechanism for Fast Packet Queuing Operations
Advanced Processor with Mechanism for Enforcing Ordering Between Information Sent on Two Independent Networks
Advanced Processor with Interfacing Messaging Network to a Cpu
Multi-Core Multi-Threaded Processing Systems with Instruction Reordering in an in-Order Pipeline
Advanced processor with mechanism for maximizing resource usage in an in-order pipeline with multiple threads
Application:
10/930,939 →
Publication:
US 2005/0044324
Advanced processor with interrupt delivery mechanism for multi-threaded multi-CPU system on a chip
Application:
10/931,003 →
Publication:
US 2005/0033889
Advanced Processor with Mechanism for Packet Distribution at High Line Rate
Prefix Matching Structure and Method for Fast Packet Switching
Mechanism for Managing Access to Resources in a Heterogeneous Data Redirection Device
Scaleable channel scheduler system and method
Application:
11/236,324 →
Publication:
US 2007/0070895
High Performance Integrated Circuit with Low Skew Clocking Networks and Improved Low Power Operating Mode Having Reduced Recovery Time
System and Method for Performing Concatentation of Diversely Routed Channels
Systems and Methods for Utilizing an Extended Translation Look-Aside Buffer Having a Hybrid Memory Structure
Advanced Processor Translation Lookaside Buffer Management in a Multithreaded System
Methods and systems for optimizing placement on a clock signal distribution network
Application:
11/710,249 →
Publication:
US 2008/0209038
Method and Apparatus for Determining Precedence in a Classification Engine
Universal Branch Identifier for Invalidation of Speculative Instructions
Method and apparatus for implementing a search engine using an SRAM
Application:
11/801,937 →
Publication:
US 2008/0281789
Masking Entries in an Age Matrix Containing Dispatch Indicators
Application:
11/820,350 →
Publication:
US 2008/0320274
System and Method for Deflate Processing Within a Compression Engine
Age Matrix for Queue Dispatch Order
Technique For Deallocation of Memory In A Multicasting Environment
Application:
11/831,884 →
Publication:
US 2007/0268901
Delegating Network Processor Operations to Star Topology Serial Bus Interfaces
Age Matrix for Queue Dispatch Order
Application:
11/847,170 →
Publication:
US 2008/0320016
System and Method for Huffman Decoding Within a Compression Engine
System and Method for Performing a Register Renaming Operation Utilizing Hardware Which Is Capable of Operating in at Least Two Modes Utilizing Registers of Multiple Widths
Patent:
7,840,783 →
Application:
11/852,916 →
Advanced Processor Messaging Apparatus Including Fast Messaging Ring Components Configured to Accomodate Point-to-Point Transfer of Non-Memory Related Messages
Advanced Processor Translation Lookaside Buffer Management in a Multithreaded System
System, method and device to encode and decode video data having multiple video data formats
System, Method and Device for Processing Macroblock Video Data
Method of Forming a Digital or Analog Multiplexing Data Frame
Advanced Processor Translation Lookaside Buffer Management in a Multithreaded System
Application:
12/018,144 →
Publication:
US 2008/0140956
Delegating Network Processor Operations to Star Topology Serial Bus Interfaces
System and Method for Parsing and Allocating a Plurality of Packets to Processor Core Threads
System, Method, and Computer Program Product for Saving and Restoring a Compression/Decompression State
Segmented Write Bitline System and Method
Patent:
7,889,582 →
Application:
12/046,675 →
System, Method, and Computer Program Product for Receiving Timer Objects from Local Lists in a Global List for Being Used to Execute Events Associated Therewith
Application:
12/055,061 →
Publication:
US 2009/0249343
System, Method, and Computer Program Product for Creating Dependencies Amongst Instructions Using Tags
Application:
12/102,473 →
Publication:
US 2009/0259827
System and Method for Offloading Packet Protocol Encapsulation from Software
Advanced Telecommunications Router and Crossbar Switch Controller
Output Queued Switch with a Parallel Shared Memory, and Method of Operating Same
System and Method for Reducing Latency Associated with Timestamps in a Multi-Core, Multi-Threaded Processor
Method and Device of Processing Video
Application:
12/202,285 →
Publication:
US 2010/0053181
Method and Device for Reordering Video Information
Advanced Processor with Credit Based Scheme for Optimal Packet Flow in a Multi-Processor System on a Chip
Device for Decoding a Video Stream and Method Thereof
Application:
12/262,211 →
Publication:
US 2010/0111166
Network-On-Chip System, Method, and Computer Program Product for Transmitting Messages Utilizing a Centralized on-Chip Shared Memory Switch
Patent:
8,671,220 →
Application:
12/325,050 →
Stacked Network Switch Using Resilient Packet Ring Communication Protocol
Patent:
8,472,312 →
Application:
12/567,595 →
Method and Apparatus for Enhanced Hashing
System and Method for Conditionally Sending a Request for Data to a Home Node
Patent:
8,438,337 →
Application:
12/571,230 →
System, Method, and Computer Program Product for Conditionally Sending a Request for Data to a Node Based on a Determination
Patent:
8,566,533 →
Application:
12/571,233 →
Advanced Processor with Fast Messaging Network Technology
Method and Apparatus for Implementing Cache Coherency of a Processor
System, Method, and Computer Program Product to Distribute Workload
Patent:
9,128,771 →
Application:
12/633,702 →
Asynchronous Transfer Mode Switching Architectures Having Connection Buffers
Application:
60/029,652 →
`Packet-based dual-ring broadband wireless network
Application:
60/256,540 →
Interfacing 622.08 MHz LVDS line interface to a 77.76 MHz SONET framer
Application:
60/273,964 →
Architecture optimized to support fixed-rate synchronous native TDM data (SONET) and burstry asynchronous data transmission over metropolitan area networking using any physical medium including but not limited to optical or wireless medium
Application:
60/276,610 →
Advanced telecommunications router and crossbar switch controller
Application:
60/333,945 →
Advanced optical transport network and components therefor
Application:
60/342,636 →
Advanced telecommunications processor
Application:
60/416,838 →
Multi-protocol serializer-deserializer (SerDes)
Application:
60/426,691 →
Technique for deallocation of memory in a multicasting environment
Application:
60/434,328 →
Advanced communication apparatus and method for verified communication
Application:
60/435,120 →
Classification of packets in a heterogeneous data redirection device
Application:
60/443,159 →
Stacked network switch using resilient packed ring communication protocol
Application:
60/463,992 →
Advanced telecommunications processor
Application:
60/490,236 →
Prefix matching structure and method for fast packet switching
Application:
60/512,121 →
High performance integrated circuit with low skew clocking networks and improved low power operating mode having reduced recovery time
Application:
60/630,527 →
System and method for providing flexible data packet processing and SONET/SDH processing
Application:
60/645,841 →
Related Assignments
(17)
Other recorded transfers of the patents in this record — the chain of ownership.
Change of Name
Apr 16, 2015
From: NETLOGIC MICROSYSTEMS, INC.
To: NETLOGIC I LLC
Reel/Frame 035443/0824 →
Assignment of Assignor's Interest
Apr 16, 2015
From: NETLOGIC I LLC
To: BROADCOM CORPORATION
Reel/Frame 035443/0763 →
Patent Security Agreement
Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
Release of Security Interest
May 6, 2016
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
To: CONEXANT SYSTEMS, INC.; CONEXANT, INC.; CONEXANT SYSTEMS WORLDWIDE, INC.; BROOKTREE BROADBAND HOLDING, INC.
Reel/Frame 038631/0452 →
Assignment of Assignor's Interest
Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
Termination and Release of Security Interest in Patents
Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
Assignment of Assignor's Interest
Jul 21, 2017
From: CONEXANT, INC.
To: CONEXANT SYSTEMS, LLC
Reel/Frame 043069/0415 →
Assignment of Assignor's Interest
Sep 7, 2017
From: CONEXANT SYSTEMS, LLC
To: SYNAPTICS INCORPORATED
Reel/Frame 043786/0267 →
Security Interest
Sep 27, 2017
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 044037/0896 →
Assignment of Assignor's Interest
Sep 24, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047022/0620 →
Corrective Assignment to Correct the Nature of Conveyance and Effective Date Previously Recorded on Reel 047022 Frame 0620. Assignor(S) Hereby Confirms the Merger.
Oct 2, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047185/0643 →
Merger
Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0026 →
Merger
Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047642/0417 →
Corrective Assignment to Correct the Effective Date Previously Recorded on Reel 047185 Frame 0643. Assignor(S) Hereby Confirms the Merger.
Oct 26, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047476/0845 →
Corrective Assignment to Correct the Effective Date of Merger Previously Recorded on Reel 047195 Frame 0026. Assignor(S) Hereby Confirms the Merger.
Nov 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047477/0423 →
Corrective Assignment to Correct the Effective Date of Merger Previously Recorded at Reel: 047185 Frame: 0643. Assignor(S) Hereby Confirms the Corrective Merger.
Nov 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047959/0296 →
Corrective Assignment to Correct the Execution Date of the Merger Previously Recorded on Reel 047642 Frame 0417. Assignor(S) Hereby Confirms the Assignment,
Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048521/0395 →