Advanced processor messaging apparatus including fast messaging ring components configured to accomodate point-to-point transfer of non-memory related messages
View Patent ↗An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
1. An advanced processor messaging apparatus, comprising:
a plurality of processor cores each having a data cache;
a data switch interconnect ring arrangement coupled to each of the processor cores and configured to pass memory related information among the plurality of processor cores;
a fast messaging network directly coupled to each of the plurality of processor cores and a plurality of communication ports; and
a plurality of fast messaging ring components, separate from the data switch interconnect ring arrangement, that is directly coupled to at least two of the plurality of processor cores, each fast messaging ring component configured to accommodate point-to-point transfer of non-memory related messages between at least two of any of the plurality of processor cores and any of the plurality of communication ports.
2. The advanced processor messaging apparatus of claim 1 ,
wherein:
the data switch interconnect ring arrangement is coupled to each of the plurality of processor cores by its respective data cache.
3. The advanced processor messaging apparatus of claim 2 , further comprising:
a level 2 cache coupled to the data switch interconnect ring arrangement and configured to store information accessible to the plurality of processor cores.
4. The advanced processor messaging apparatus of claim 3 ,
further comprising:
an interface switch interconnect coupled to the fast messaging network and the plurality of communication ports and configured to pass information among the fast messaging network and the plurality of communication ports.
5. The advanced processor messaging apparatus of claim 4 ,
further comprising:
a memory bridge coupled to the data switch interconnect ring arrangement and at least one communication port, and configured to communicate with the data switch interconnect ring arrangement and the at least one communication port.
6. The advanced processor messaging apparatus of claim 5 ,
further comprising:
a super memory bridge coupled to the data switch interconnect ring arrangement, the interface switch interconnect and the at least one communication port, and configured to communicate with the data switch interconnect ring arrangement, the interface switch interconnect and the at least one communication port.
7. The advanced processor messaging apparatus of claim 4 ,
further comprising:
a super memory bridge coupled to the data switch interconnect ring arrangement, the interface switch interconnect and at least one communication port, and configured to communicate with the data switch interconnect ring arrangement, the interface switch interconnect and the at least one communication port.
8. The advanced processor messaging apparatus of claim 3 ,
further comprising:
a memory bridge coupled to the data switch interconnect ring arrangement and at least one communication port, and configured to communicate with the data switch interconnect ring arrangement and the at least one communication port.
9. The advanced processor messaging apparatus of claim 8 ,
further comprising:
a super memory bridge coupled to the data switch interconnect ring arrangement, an interface switch interconnect and the at least one communication port, and configured to communicate with the data switch interconnect ring arrangement, the interface switch interconnect and the at least one communication port.
10. The advanced processor messaging apparatus of claim 3 ,
further comprising:
a super memory bridge coupled to the data switch interconnect ring arrangement, an interface switch interconnect and at least one communication port, and configured to communicate with the data switch interconnect ring arrangement, the interface switch interconnect and the at least one communication port.
11. The advanced processor messaging apparatus of claim 2 ,
further comprising:
an interface switch interconnect coupled to the fast messaging network and the plurality of communication ports and configured to pass information among the fast messaging network and the plurality of communication ports.
12. The advanced processor messaging apparatus of claim 11 ,
further comprising:
a memory bridge coupled to the data switch interconnect ring arrangement and at least one communication port, and configured to communicate with the data switch interconnect ring arrangement and the at least one communication port.
13. The advanced processor messaging apparatus of claim 12 ,
further comprising:
a super memory bridge coupled to the data switch interconnect ring arrangement, the interface switch interconnect and the at least one communication port, and configured to communicate with the data switch interconnect ring arrangement, the interface switch interconnect and the at least one communication port.
14. The advanced processor messaging apparatus of claim 11 ,
further comprising:
a super memory bridge coupled to the data switch interconnect ring arrangement, the interface switch interconnect and at least one communication port, and configured to communicate with the data switch interconnect ring arrangement, the interface switch interconnect and the at least one communication port.
15. The advanced processor messaging apparatus of claim 2 ,
further comprising:
a memory bridge coupled to the data switch interconnect ring arrangement and at least one communication port, and configured to communicate with the data switch interconnect ring arrangement and the at least one communication port.
16. The advanced processor messaging apparatus of claim 15 ,
further comprising:
a super memory bridge coupled to the data switch interconnect ring arrangement, an interface switch interconnect and the at least one communication port, and configured to communicate with the data switch interconnect ring arrangement, the interface switch interconnect and the at least one communication port.
17. The advanced processor messaging apparatus of claim 2 ,
further comprising:
a super memory bridge coupled to the data switch interconnect ring arrangement, an interface switch interconnect and at least one communication port, and configured to communicate with the data switch interconnect ring arrangement, the interface switch interconnect and the at least one communication port.
18. The advanced processor messaging apparatus of claim 1 ,
further comprising:
a level 2 cache coupled to the data switch interconnect ring arrangement and configured to store information accessible to the plurality of processor cores.
19. The advanced processor messaging apparatus of claim 18 ,
further comprising:
an interface switch interconnect coupled to the fast messaging network and the plurality of communication ports and configured to pass information among the fast messaging network and the plurality of communication ports.
20. The advanced processor messaging apparatus of claim 19 ,
further comprising:
a memory bridge coupled to the data switch interconnect ring arrangement and at least one communication port, and configured to communicate with the data switch interconnect ring arrangement and the at least one communication port.
21. The advanced processor messaging apparatus of claim 20 ,
further comprising:
a super memory bridge coupled to the data switch interconnect ring arrangement, the interface switch interconnect and the at least one communication port, and configured to communicate with the data switch interconnect ring arrangement, the interface switch interconnect and the at least one communication port.
22. The advanced processor messaging apparatus of claim 19
further comprising:
a super memory bridge coupled to the data switch interconnect ring arrangement, the interface switch interconnect and at least one communication port, and configured to communicate with the data switch interconnect ring arrangement, the interface switch interconnect and the at least one communication port.
23. The advanced processor messaging apparatus of claim 18 ,
further comprising:
a memory bridge coupled to the data switch interconnect ring arrangement and at least one communication port, and configured to communicate with the data switch interconnect ring arrangement and the at least one communication port.
24. The advanced processor messaging apparatus of claim 23 ,
further comprising:
a super memory bridge coupled to the data switch interconnect ring arrangement, an interface switch interconnect and the at least one communication port, and configured to communicate with the data switch interconnect ring arrangement, the interface switch interconnect and the at least one communication port.
25. The advanced processor messaging apparatus of claim 18 ,
further comprising:
a super memory bridge coupled to the data switch interconnect ring arrangement, an interface switch interconnect and at least one communication port, and configured to communicate with the data switch interconnect ring arrangement, the interface switch interconnect and the at least one communication port.
26. The advanced processor messaging apparatus of claim 1 ,
further comprising:
an interface switch interconnect coupled to the fast messaging network and the plurality of communication ports and configured to pass information among the fast messaging network and the plurality of communication ports.
27. The advanced processor messaging apparatus of claim 26 ,
further comprising:
a memory bridge coupled to the data switch interconnect ring arrangement and at least one communication port, and configured to communicate with the data switch interconnect ring arrangement and the at least one communication port.
28. The advanced processor messaging apparatus of claim 27 ,
further comprising:
a super memory bridge coupled to the data switch interconnect ring arrangement, the interface switch interconnect and the at least one communication port, and configured to communicate with the data switch interconnect ring arrangement, the interface switch interconnect and the at least one communication port.
29. The advanced processor messaging apparatus of claim 26 ,
further comprising:
a super memory bridge coupled to the data switch interconnect ring arrangement, the interface switch interconnect and at least one communication port, and configured to communicate with the data switch interconnect ring arrangement, the interface switch interconnect and the at least one communication port.
30. The advanced processor messaging apparatus of claim 1 ,
further comprising:
a memory bridge coupled to the data switch interconnect ring arrangement and at least one communication port, and configured to communicate with the data switch interconnect ring arrangement and the at least one communication port.
31. The advanced processor messaging apparatus of claim 30 ,
further comprising;
a super memory bridge coupled to the data switch interconnect ring arrangement, an interface switch interconnect and the at least one communication port, and configured to communicate with the data switch interconnect ring arrangement, the interface switch interconnect and the at least one communication port.
32. The advanced processor messaging apparatus of claim 1 ,
further comprising:
a super memory bridge coupled to the data switch interconnect ring arrangement, an interface switch interconnect and at least one communication port, and configured to communicate with the data switch interconnect ring arrangement, the interface switch interconnect and the at least one communication port.
33. The advanced processor messaging apparatus of claim 1 , wherein the transfer of the non-memory related messages is accomplished without the non-memory related messages passing through an instruction cache.
34. The advanced processor messaging apparatus of claim 1 , wherein the transfer of the non-memory related messages is accomplished without the non-memory related messages passing through the data cache.
35. The advanced processor messaging apparatus of claim 1 , wherein the non-memory related messages comprise identification fields including at least a thread field, a source field, and a destination field.
36. The advanced processor messaging apparatus of claim 1 , wherein the non-memory related messages include at least one of a message size indicator and message data.
37. The advanced processor messaging apparatus of claim 1 , wherein the fast messaging network has a ring configuration.