System and method for reducing latency associated with timestamps in a multi-core, multi-threaded processor
View Patent ↗A system and method are provided for reducing a latency associated with timestamps in a multi-core, multi threaded processor. A processor capable of simultaneously processing a plurality of threads is provided. The processor includes a plurality of cores, a plurality of network interfaces for network communication, and a timer circuit for reducing a latency associated with timestamps used for synchronization of the network communication utilizing a precision time protocol.
1. An apparatus, comprising:
a processor configured to process a plurality of threads, the processor including:
a plurality of cores,
a plurality of network interfaces for network communication, and
a timer circuit corresponding to at least one of the plurality of cores to reduce a latency associated with timestamps used for synchronization of the network communication, in which the at least one of the plurality of cores, by using the timer circuit included within the processor, generates and communicates the timestamps directly from the at least one of the plurality of cores to at least one of the plurality of network interfaces.
2. The apparatus of claim 1 , wherein the latency includes memory latency.
3. The apparatus of claim 1 , wherein the latency includes interrupt latency.
4. The apparatus of claim 3 , wherein the interrupt latency is eliminated by avoiding use of interrupts.
5. The apparatus of claim 1 , wherein the at least one of the plurality of cores is coupled to a network for communicating the timestamps.
6. The apparatus of claim 1 , wherein the timer circuit is configured to utilize a time-transfer protocol defined by IEEE 1588.
7. The apparatus of claim 1 , wherein the timer circuit is programmable.
8. The apparatus of claim 1 , wherein the timer circuit is fed by a plurality of clock frequency sources.
9. The apparatus of claim 1 , wherein the timer circuit includes a divider, a multiplier, and an offset sub-circuit.
10. The apparatus of claim 1 , wherein the timer circuit is configured to synchronize the network communication across each of the plurality of network interfaces.
11. The apparatus of claim 1 , wherein the cores are each configured to generate a precision time protocol packet including one of the timestamps.
12. The apparatus of claim 11 , wherein the cores are each configured to generate the precision time protocol packet including one of the timestamps, utilizing a single register write.
13. The apparatus of claim 1 , wherein a precision time protocol packet including one of the timestamps is configured to be processed by any selected one of the cores.
14. The apparatus of claim 1 , wherein any of the cores is configured to manage any of the network interfaces.
15. The apparatus of claim 1 , wherein the network interfaces include a master network interface and a slave network interface.
16. A method of operating a processor including a plurality of cores and a plurality of network interfaces, the method comprising:
utilizing a timer circuit corresponding to at least one of the plurality of cores to reduce a latency associated with timestamps used for synchronization of network communication, in which the at least one of the plurality of cores, by using the timer circuit included within the processor, generates and communicates the timestamps directly from the at least one of the plurality of cores to at least one of the plurality of network interfaces; and
transferring the timestamps between the plurality of cores and the plurality of network interfaces.
17. The method of claim 16 , wherein the latency includes memory latency.
18. The method of claim 16 , wherein the latency includes interrupt latency.
19. The method of claim 18 , wherein the interrupt latency is eliminated by avoiding use of interrupts.
20. The method of claim 16 , wherein the at least one of the plurality of cores is coupled to a network for communicating the timestamps.