Advanced processor with mechanism for fast packet queuing operations
View Patent ↗An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
1. An advanced processor, comprising:
a packet distribution engine (PDE) configured to receive a plurality of packets from a networking input and to distribute the plurality of packets to a packet processing system having a plurality of processor cores;
a packet ordering mechanism configured to receive processed packets from the packet processing system and to provide the processed packets to a networking output; and
a fast messaging network (FMN) coupled to the PDE, said FMN also coupled to at least two of the processor cores and configured to link said at least two of the processor cores together such that at least one processor core can send data to another processor core without going through memory.
2. The advanced processor of claim 1 , wherein:
each processor core is configured to support a plurality of operating systems.
3. The advanced processor of claim 1 , wherein:
each processor core is configured to execute multiple threads.
4. The advanced processor of claim 3 , wherein:
the multiple threads includes four threads.
5. The advanced processor of claim 1 , wherein:
the networking input is configured to support at least RGMII, XGMII, and SPI-4.2 interfaces.
6. The advanced processor of claim 1 , wherein:
the networking output is configured to support at least RGMII, XGMII, and SPI-4.2 interfaces.
7. The advanced processor of claim 1 , wherein:
the packet ordering mechanism includes a software implementation.
8. The advanced processor of claim 1 , wherein:
the packet ordering mechanism includes a packet ordering device (POD) hardware implementation.
9. The advanced processor of claim 1 , wherein once a thread has completed processing one of the plurality of packets, the thread forwards a packet descriptor and an original sequence number to the packet ordering mechanism.
10. The advanced processor of claim 9 , wherein the packet ordering mechanism releases the one of the plurality of packets to the networking output in an order determined by the original sequence number assigned by the networking input.
11. The advanced processor of claim 1 , wherein the packet ordering mechanism receives the processed packets in a random order.
12. The advanced processor of claim 1 , wherein the FMN is a ring configuration.
13. The advanced processor of claim 1 , wherein the FMN is directly coupled to the PDE.
14. A method of controlling a flow of packets, the method comprising the steps of:
receiving a plurality of packets from a networking input;
placing the plurality of packets in a packet distribution engine (PDE);
distributing the plurality of packets from the PDE to a packet processing system having a plurality of processor cores; receiving processed packets from the packet processing system in a packet ordering mechanism; and
providing the processed packets to a networking output;
wherein a fast messaging network (FMN) is coupled to the PDE, the packet processing system, the packet ordering mechanism, and the networking output, said FMN also coupled to at least two of the processor cores and configured to link said at least two of the processor cores together such that at least one processor core can send data to another processor core without going through memory.
15. The method of claim 14 , wherein:
each processor core is configured to support a plurality of operating systems.
16. The method of claim 14 , wherein:
each processor core is configured to execute multiple threads.
17. The method of claim 16 , wherein:
the multiple threads includes four threads.
18. The method of claim 14 , wherein:
the networking input is configured to support at least RGMII, XGMII, and SPI-4.2 interfaces.
19. The method of claim 14 , wherein:
the networking output is configured to support at least RGMII, XGMII, and SPI-4.2 interfaces.
20. The method of claim 14 , wherein:
the step of distributing includes using the fast messaging network (FMN) coupled to the PDE and the packet processing system.
21. The method of claim 14 , wherein:
the step of providing includes using the fast messaging network (FMN) coupled to the packet ordering mechanism and the networking output.
22. The method of claim 14 , wherein:
the packet ordering mechanism includes a software implementation.
23. The method of claim 14 , wherein:
the packet ordering mechanism includes a packet ordering device (POD) hardware implementation.
24. An advanced processing system, comprising:
a plurality of processor cores, each processor core being configured to execute multiple threads and to process a plurality of packets, the plurality of packets being received by a networking input, the plurality of packets being further provided to the plurality of processor cores by a packet distribution engine (PDE);
a packet ordering mechanism configured to receive processed packets from the plurality of processor cores and to provide the processed packets to a networking output; and
a fast messaging network (FMN) coupled to the PDE, said FMN also coupled to at least two of the processor cores and configured to link said at least two of the processor cores together such that at least one processor core can send data to another processor core without going through memory.
25. The system of claim 24 , wherein:
each processor core is configured to support a plurality of operating systems.
26. The system of claim 24 , wherein:
the multiple threads includes four threads.
27. The system of claim 24 , wherein:
the networking input is configured to support at least RGMII, XGMII, and SPI-4.2 interfaces.
28. The system of claim 24 , wherein:
the networking output is configured to support at least RGMII, XGMII, and SPI-4.2 interfaces.
29. The system of claim 24 , wherein:
the packet ordering mechanism includes a software implementation.
30. The system of claim 24 , wherein:
the packet ordering mechanism includes a packet ordering device (POD) hardware implementation.
31. The system of claim 24 , wherein:
the plurality of processor cores includes eight processor cores.
32. An advanced processor, comprising:
a packet processing system comprising a plurality of processor cores, each processor core configured to execute multiple threads;
a fast messaging network coupled to the plurality of processor cores;
a packet distribution engine (PDE) coupled to the fast messaging network, said PDE configured to receive a plurality of packets from a networking input and to distribute the plurality of packets to the packet processing system, the PDE and fast messaging network configured to distribute each packet to a selected thread of one of the plurality of processor cores, wherein the selected thread progresses among the multiple threads, said fast messaging network coupled to at least two of the processor cores and configured to link said at least two of the processor cores together such that at least one processor core can send data to another processor core without going through memory; and
a packet ordering system coupled to the fast messaging network and configured to receive packets from the packet processing system and to provide the processed packets to a networking output.
33. The advanced processor of claim 32 , wherein the packet ordering mechanism is separate from the packet processing system.