Advanced processor translation lookaside buffer management in a multithreaded system
View Patent ↗An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
1. An advanced processor for executing software applications on different operating systems, comprising:
a plurality of processor cores each configured to execute multiple threads,
a memory management unit (MMU) coupled to said processor cores having first, second, and third translation-lookaside buffer (TLB) portions operable in at least a partitioned mode and a global mode;
each TLB portion having a plurality of entries, wherein the first TLB portion is configured for instructions, the second TLB portion is configured for data, and at least one of the plurality of entries is tagged with a thread identification;
wherein: the first and second TLB portions are configured to allow a thread to freely allocate entries in the respective first or second TLB portion in either mode and to restrict access to the allocated entries to the thread in the partitioned mode; and the third TLB portion is configured to restrict the thread to allocated entries in an exclusive subset of the third TLB portion and to restrict access to the allocated entries to the thread in the partitioned mode and the third TLB portion is configured to allow the thread to freely allocate entries in the third TLB portion in the global mode;
wherein each of the plurality of processor cores includes a data cache and an instruction cache;
a plurality of different operating systems each running on one of the plurality of processor cores;
a data switch interconnect ring arrangement directly coupled with the data cache of each of the plurality of processor cores and configured to pass memory related information among the plurality of processor cores; and
a messaging network directly coupled with the instruction cache of each of the plurality of processor cores and a plurality of communication ports.
2. The advanced processor of claim 1 , wherein:
a first processor core is configured to run a first operating system;
a second processor core is configured to run a second operating system different from the first operating system; and
a third processor core is configured to run a third operating system different from the first operating system and the second operating system.
3. The advanced processor of claim 2 , further comprising:
a level 2 cache coupled to the data switch interconnect and configured to store memory related information accessible to the plurality of processor cores.
4. The advanced processor of claim 1 , wherein:
a first thread is configured to run a first operating system;
a second thread is configured to run a second operating system different from the first operating system; and
a third thread is configured to run a third operating system different from the first operating system and the second operating system.
5. The advanced processor of claim 1 , wherein:
a first core is configured to run a first operating system; and
a first thread is configured to run a second operating system different from the first operating system.
6. The advanced processor of claim 1 , further comprising:
a level 2 cache coupled to the data switch interconnect and configured to store memory related information accessible to the plurality of processor cores.
7. An advanced processor for executing software applications on different operating systems, comprising:
a plurality of processor cores each configured to execute multiple threads wherein each of the plurality of processor cores includes a data cache and an instruction cache;
a memory management unit (MMU) coupled to said processor cores having first, second, and third translation-lookaside buffer (TLB) portions operable in at least a partitioned mode and a global mode;
each TLB portion having a plurality of entries, wherein the first TLB portion is configured for instructions, the second TLB portion is configured for data, and at least one of the plurality of entries is tagged with a thread identification;
wherein: the first and second TLB portions are configured to allow a thread to freely allocate entries in the respective first or second TLB portion in either mode and to restrict access to the allocated entries to the thread in the partitioned mode; and the third TLB portion is configured to restrict the thread to allocated entries in an exclusive subset of the third TLB portion and to restrict access to the allocated entries to the thread in the partitioned mode and the third TLB portion is configured to allow the thread to freely allocate entries in the third TLB portion in the global mode;
a plurality of different operating systems each running on one of the plurality of processor cores;
a data switch interconnect ring arrangement coupled with each of the plurality of processor cores and configured to pass memory related information among the processor cores, wherein the data switch interconnect is directly coupled with each of the plurality of processor cores by a respective data cache;
a messaging network coupled with each of the plurality of processor cores and a plurality of communication ports wherein the messaging network is directly coupled with each of the plurality of processor cores by a respective instruction cache;
a level 2 cache coupled to the data switch interconnect and configured to store memory related information accessible to the plurality of processor cores.
8. An advanced processor for executing software applications on different operating systems, comprising:
a plurality of processor cores each configured to execute multiple threads; a memory management unit (MMU) coupled to said processor cores having first, second, and third translation-lookaside buffer (TLB) portions operable in at least a partitioned mode and a global mode;
each TLB portion having a plurality of entries, wherein the first TLB portion is configured for instructions, the second TLB portion is configured for data, and at least one of the plurality of entries is tagged with a thread identification;
wherein: the first and second TLB portions are configured to allow a thread to freely allocate entries in the respective first or second TLB portion in either mode and to restrict access to the allocated entries to the thread in the partitioned mode; and the third TLB portion is configured to restrict the thread to allocated entries in an exclusive subset of the third TLB portion and to restrict access to the allocated entries to the thread in the partitioned mode and the third TLB portion is configured to allow the thread to freely allocate entries in the third TLB portion in the global mode;
a plurality of operating systems running on the processor cores;
a data switch interconnect coupled to each of the processor cores and configured to pass information among the processor cores; and
a messaging network coupled to each of the processor cores and a plurality of communication ports.
9. The advanced processor of claim 8 , in which the processor cores transition between multiple threads run by said different applications running on said different operating systems using a multithreaded round robin, weighted round robin, or eager round robin scheduler.
10. The advanced processor of claim 9 , in which at least one of said TLB portions allocates entries using a not-recently-used (NRU) algorithm.