Advanced processor scheduling in a multithreaded system
View Patent ↗An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
1. A single-chip telecommunications processor, comprising:
a plurality of processor cores configured to execute multiple threads;
at least one scheduler being coupled to the plurality of processor cores, wherein
the at least one scheduler configured to receive a plurality of packet segments arranged in a plurality of packet threads of the multiple threads and to provide a single issue thread of the plurality of packet segments by issuing a packet segment from each of the plurality of packet threads in a sequence,
a subsequent packet segment is chosen from a first positional packet thread for each of a first predetermined number of cycles,
the subsequent packet segment is chosen from a second positional packet thread for each of a second predetermined number of cycles prior to reaching the first predetermined number of cycles, if a stall condition is detected in the first positional packet thread, rather than from an empty thread among the multiple threads, and
the single-chip telecommunications processor is configured for allowing for restarting from a pipeline stall point rather than flushing the pipeline to effect a pipeline stall when the pipeline stall is needed or requested;
a first-in first-out buffer that is coupled to a fetch module and is configured to receive the plurality of packet segments arranged in the plurality of packet threads, in which at least one of the plurality of packet segments in the first-in first-out buffer is scheduled out of a first-in first-out order by the at least one scheduler based at least in part upon a signal set by the fetch module to the first-in first-out buffer; and
a hazard detection logic module coupled to the fetch module and is configured to determine whether a stall is needed or requested, wherein
if a stall is needed or requested, the hazard detection logic module sends a signal to the first-in first-out buffer to restart execution from the pipeline stall point, and
if no stall is needed or requested, one of the plurality of packet segments that causes the pipeline stall is discarded from the first-in first-out buffer.
2. The single-chip telecommunications processor of claim 1 , wherein a cache miss results in the stall condition.
3. The single-chip telecommunications processor of claim 1 , in which at least some of the plurality of processor cores comprise an architecture and an instruction set of MIPS, x86, PowerPC, or ARM.
4. The single-chip telecommunications processor of claim 1 , in which at least some of the plurality of processor cores comprise a MIPS architecture and instruction set.
5. The single-chip telecommunications processor of claim 1 , in which at least some of the plurality of processor cores are characterized by supporting a 4-way multithreaded pipeline.
6. The single-chip telecommunications processor of claim 1 , comprising eight, more than eight, or fewer than eight processor cores.
7. The single-chip telecommunications processor of claim 1 , in which one of the plurality of packet segments that causes the pipeline stall is discarded from the first-in first-out buffer.
8. The single-chip telecommunications processor of claim 1 , in which the single-chip telecommunications processor is configured such that an ordering is utilized to improve a pipeline efficiency when the stall condition is encountered, requested, or needed.
9. A method of scheduling threads in a telecommunications processor comprised of a plurality of processor cores that are configured to execute multiple threads, comprising:
receiving a plurality of packet segments arranged in a plurality of packet threads of the multiple threads by configuring at least one scheduler;
providing a single issue thread of the plurality of packet segments by issuing a packet segment from each of the plurality of packet threads in a sequence, wherein
the subsequent packet segment is chosen from a second positional packet thread for each of a second predetermined number of cycles prior to reaching the first predetermined number of cycles, if a stall condition is detected in the first positional packet thread, rather than from an empty thread among the multiple threads,
the single-chip telecommunications processor is configured for allowing for restarting from a pipeline stall point rather than flushing the pipeline to effect a pipeline stall when the pipeline stall is needed or requested;
receiving the plurality of packet segments arranged in the plurality of packet threads at a first-in first-out buffer that is coupled to a fetch logic, in which
at least one of the plurality of packet segments in the first-in first-out buffer is scheduled out of a first-in first-out order by the at least one scheduler based at least in part upon a signal set by the fetch module to the first-in first-out buffer; and
determining whether a stall is needed or requested by using a hazard detection process that is coupled to the fetch process, wherein
if a stall is needed or requested, the hazard detection logic module sends a signal to the first-in first-out buffer to restart execution from the pipeline stall point, and
if no stall is needed or requested, one of the plurality of packet segments that causes the pipeline stall is discarded from the first-in first-out buffer.
10. The method of claim 9 , wherein the act of providing the single issue thread of the plurality of packet segments includes determining a subsequent packet thread by sequencing through each successive next positional thread until an available packet segment is found.
11. The method of claim 9 , wherein the act of receiving the plurality of packet segments includes receiving the plurality of packet segments from same packet thread.
12. The method of claim 9 , wherein the act of providing the single issue thread of the plurality of packet segments includes processing the plurality of packet segments using an eager round robin technique.