Advanced processor translation lookaside buffer management in a multithreaded system
View Patent ↗An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
1. An advanced processor, comprising:
a plurality of processor cores configured to execute multiple threads;
a data switch interconnect ring arrangement coupled to the plurality of processor cores and configured to pass information among the plurality of processor cores;
a fast messaging network coupled to the plurality of processor cores and a plurality of communication ports;
a plurality of fast messaging ring components, separate from the data switch interconnect ring arrangement, coupled to at least two of the processor cores, wherein at least one of the plurality of fast messaging ring components is configured to accommodate point-to-point transfer of messages between at least two of the processor cores and any of the plurality of communication ports;
a memory management unit (MMU) coupled to at least one of the plurality of processor cores, the MMU having first, second, and third translation-lookaside buffer (TLB) portions operable in at least two modes, each TLB portion comprises a plurality of entries, wherein the first TLB portion is configured for instructions, the second TLB portion is configured for data, and at least one of the plurality of entries is tagged with a thread identification, wherein the at least two modes include a partitioned mode and a global mode; and
wherein the first and second TLB portions are configured to allow a thread to freely allocate entries in the first and second TLB portions in either mode and to restrict access to the allocated entries to the thread in the partitioned mode; and the third TLB portion is configured to restrict the thread to allocated entries in an exclusive subset of the third TLB portion and to restrict access to the allocated entries to the thread in the partitioned mode, and the third TLB portion is configured to allow the thread to freely allocate entries in the third TLB portion in the global mode.
2. The advanced processor of claim 1 , wherein:
a first processor core is configured to run a first operating system;
a second processor core is configured to run a second operating system different from the first operating system; and
a third processor core is configured to run a third operating system different from the first operating system and the second operating system.
3. The advanced processor of claim 2 , further comprising:
a level 2 cache coupled to the data switch interconnect ring arrangement and configured to store information accessible to the plurality of processor cores.
4. The advanced processor of claim 1 , wherein:
a first thread is configured to run a first operating system;
a second thread is configured to run a second operating system different from the first operating system; and
a third thread is configured to run a third operating system different from the first operating system and the second operating system.
5. The advanced processor of claim 1 , wherein:
a first core is configured to run a first operating system; and
a first thread is configured to run a second operating system different from the first operating system.
6. The advanced processor of claim 1 , wherein:
the data switch interconnect ring arrangement is coupled to each of the plurality of processor cores by a respective data cache; and
the fast messaging network is coupled to each of the plurality of processor cores by a respective instruction cache.
7. The advanced processor of claim 1 , further comprising:
a level 2 cache coupled to the data switch interconnect ring arrangement and configured to store information accessible to the plurality of processor cores.
8. The advanced processor of claim 1 , further comprising:
an interface switch interconnect coupled to the fast messaging network and the plurality of communication ports and configured to pass information among the fast messaging network and the plurality of communication ports.
9. The advanced processor of claim 1 , further comprising:
a memory bridge coupled to the data switch interconnect ring arrangement and at least one communication port, and configured to communicate with the data switch interconnect ring arrangement and the at least one communication port.
10. The advanced processor of claim 1 , further comprising:
a super memory bridge coupled to the data switch interconnect ring arrangement, an interface switch interconnect, and at least one communication port, and configured to communicate with the data switch interconnect ring arrangement, the interface switch interconnect, and the at least one communication port.
11. The advanced processor of claim 1 , wherein the transfer of the messages is accomplished without the messages passing through an instruction cache.
12. The advanced processor of claim 1 , wherein the transfer of the messages is accomplished without the messages passing through a data cache.
13. The advanced processor of claim 1 , wherein the messages comprise identification fields including at least a thread field, a source field, and a destination field.
14. The advanced processor of claim 1 , wherein the messages include at least one of a message size indicator and message data.
15. The advanced processor of claim 1 , wherein the fast messaging network has a ring configuration.
16. The advanced processor of claim 1 , wherein the MMU operates in the at least two modes.
17. The advanced processor of claim 1 , wherein the first and second TLB portions include 32 entries and the third TLB portion includes 128 entries.
18. The advanced processor of claim 1 , wherein a not recently-used (NRU) algorithm is used for entry allocation in the first and second TLB portions.
19. The advanced processor of claim 1 , wherein at least one of the processor cores is directly coupled to the fast messaging network.
20. An apparatus, comprising:
a plurality of processor cores configured for executing multiple threads;
a data switch interconnect ring arrangement coupled to the plurality of processor cores and configured to pass information among the plurality of processor cores;
a fast messaging network coupled to the plurality of processor cores and a plurality of communication ports;
said fast messaging network comprising a plurality of fast messaging ring components, separate from the data switch interconnect ring arrangement, coupled to at least two of the plurality of processor cores, the fast messaging ring components including a transmit queue and a receive queue for each of the processor cores, wherein at least one of the plurality of fast messaging ring components is configured to accommodate point-to-point transfer of messages between at least two of any of the plurality of processor cores and any of the plurality of communication ports without going through memory external to the fast messaging ring components;
a memory management unit (MMU) coupled to at least one of the plurality of processor cores, the MMU having a translation-lookaside buffer (TLB);
wherein said TLB comprises first, second, and third translation-lookaside buffer (TLB) portions operable in at least two modes, the first, second and third TLB portions comprise a plurality of entries and the first TLB portion is configured for instructions, the second TLB portion is configured for data, and at least one of the plurality of entries is tagged with a thread identification; and
wherein said first and second TLB portions are configured to allow a thread to freely allocate entries in the first and second TLB portions in either mode and to restrict access to the allocated entries to the thread in the partitioned mode; and the third TLB portion is configured to restrict the thread to allocated entries in an exclusive subset of the third TLB portion and to restrict access to the allocated entries to the thread in the partitioned mode, and the third TLB portion is configured to allow the thread to freely allocate entries in the third TLB portion in the global mode.
21. The apparatus of claim 20 , wherein at least one of the processor cores is directly coupled to the fast messaging network.
22. The apparatus of claim 20 , wherein:
at least one of the plurality of processor cores is configured to run a first operating system; and
at least one of the multiple threads is configured to run a second operating system different from the first operating system.
23. The apparatus of claim 20 , wherein at least one of the plurality of fast messaging ring components is configured to accommodate point-to-point transfer of messages between at least two of the processor cores such that at least one processor core can send data to another processor core without going through memory external to the fast messaging ring components.