Segmented write bitline system and method
View Patent ↗A memory device is provided for performing writing operations on memory cells while maintaining a stability thereof. A memory array is provided including a plurality of memory cells. Additionally, segmented write bitlines are provided for performing writing operations on the memory cells while maintaining a stability thereof.
1. A memory device, comprising:
a memory array including a plurality of memory cells coupled to a circuit;
a global bitline for providing a global bitline command to the circuit; and
a local bitline for providing a local bitline command from the circuit for performing writing operations on the memory cells while maintaining distinguishable logic value of a masked bit in the memory cells, wherein the circuit performs a mask operation in conjunction with the writing operations based at least in part on the global bitline command, wherein the mask operation comprises an operation where one or more selected bits are written to the memory cells while other bits of the memory cells are not affected.
2. The memory device of claim 1 , wherein the memory array includes static random access memory (SRAM).
3. The memory device of claim 1 , wherein the local bitline has a lower capacitance than the global bitline.
4. The memory device of claim 1 , wherein the local bitline supports at least three input states.
5. The memory device of claim 1 , wherein the circuit is configured for maintaining the stability of the memory cells.
6. The memory device of claim 5 , wherein the circuit includes a plurality of transistors configured for maintaining the stability.
7. The memory device of claim 5 , wherein the circuit includes a plurality of inverters configured for maintaining the stability.
8. A method, comprising:
providing a memory array including a plurality of memory cells coupled to a circuit;
utilizing a global bitline to provide a global bitline command to the circuit; and performing writing operations on the memory cells while maintaining a distinguishable logic value of a masked bit in the memory cells by utilizing a local bitline to provide a local bitline command from the circuit, wherein the circuit performs a mask operation in conjunction with the writing operations based at least in part upon the global bitline command, wherein the mask operation comprises an operation where one or more selected bits are written to the memory cells while other bits of the memory cells are not affected.
9. The method of claim 8 , wherein the memory array includes static random access memory (SRAM).
10. The method of claim 8 , wherein the local bitline has a lower capacitance than the global bitline.
11. The method of claim 8 , wherein the local bitline supports at least three input states.
12. The method of claim 8 , wherein the circuit is configured for maintaining the stability of the memory cells.
13. The method of claim 12 , wherein the circuit includes a plurality of transistors configured for maintaining the stability.
14. The method of claim 12 , wherein the circuit includes a plurality of inverters configured for maintaining the stability.
15. A system, comprising:
a bus;
a processor in communication with the bus;
memory in communication with the bus, the memory including a memory array including a plurality of memory cells coupled to a circuit;
a global bitline for providing a global bitline command to the circuit, and a local bitline for providing a local bitline command from the circuit for performing writing operations on the memory cells while maintaining a distinguishable logic value of a masked bit in the memory cells, wherein the circuit performs a mask operation in conjunction with the writing operations based at least in part upon the global bitline command, wherein the mask operation comprises an operation where one or more selected bits are written to the memory cells while other bits of the memory cells are not affected.
16. The system of claim 15 , wherein the memory array includes static random access memory (SRAM).
17. The system of claim 15 , wherein the local bitline has a lower capacitance than the global bitline.
18. The system of claim 15 , wherein the local bitline supports at least three input states.
19. The system of claim 15 , wherein the circuit is configured for maintaining the stability of the memory cells.
20. The system of claim 19 , wherein the circuit includes a plurality of transistors configured for maintaining the stability.
21. The memory device of claim 19 , wherein the circuit includes a plurality of inverters configured for maintaining the stability.