Advanced processor with cache coherency
View Patent ↗An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
1. An advanced processor, comprising:
a plurality of processor cores each having a data cache;
a data switch interconnect directly coupled with the data cache of each of the plurality of processor cores and configured to pass memory related information among the plurality of processor cores;
a level 2 cache coupled to the data switch interconnect and configured to employ a coherency technique that allows the sharing of dirty cache lines across the plurality of processor cores, wherein the data switch interconnect includes a ring arrangement with a plurality of ring elements each coupled to a respective data cache of each of the plurality of processor cores and a respective portion of the level 2 cache;
a fast messaging ring component directly coupled the plurality of processor cores, the fast messaging ring component including a ring input coupled to an insertion queue and a receive queue; and
a plurality of communication ports coupled with the fast messaging ring component for providing communication with a plurality of high-speed processor I/O devices.
2. The advanced processor of claim 1 , wherein the level 2 cache coupled to the data switch interconnect is configured to share the dirty cache lines across the plurality of processor cores.
3. The advanced processor of claim 2 , wherein:
the level 2 cache is configured to employ a coherency technique based on a MOSI (Modified, Own, Shared, Invalid) protocol or a MOESI (Modified, Own, Exclusive, Shared, Invalid) protocol.
4. The advanced processor of claim 3 , further comprising:
a memory bridge coupled to the data switch interconnect and at least one communication port, and configured to communicate with the data switch interconnect and the at least one communication port.
5. The advanced processor of claim 2 , further comprising:
a memory bridge coupled to the data switch interconnect and at least one communication port, and configured to communicate with the data switch interconnect and the at least one communication port.
6. The advanced processor of claim 2 wherein the plurality of processor cores runs at least one different operating system.
7. The advanced processor of claim 6 wherein the plurality of processor cores operates at least one different clock speed.
8. The advanced processor of claim 1 , wherein:
the level 2 cache is configured to employ a coherency technique based on a MOSI (Modified, Own, Shared, Invalid) protocol or a MOESI (Modified, Own, Exclusive, Shared, Invalid) protocol.
9. The advanced processor of claim 8 , further comprising:
a memory bridge coupled to the data switch interconnect and at least one communication port, and configured to communicate with the data switch interconnect and the at least one communication port.
10. The advanced processor of claim 1 , further comprising:
a memory bridge coupled to the data switch interconnect and at least one communication port, and configured to communicate with the data switch interconnect and the at least one communication port.
11. The advanced processor of claim 1 wherein the plurality of processor cores runs at least one different operating system.
12. The advanced processor of claim 11 wherein the plurality of processor cores operates at least one different clock speed.
13. The advanced processor of claim 1 , wherein the fast messaging ring component is an agent on a fast messaging network.
14. The advanced processor of claim 1 , wherein the fast messaging ring component is separate from the data switch interconnect.
15. The advanced processor of claim 1 , wherein the fast messaging ring component further includes a multiplexer having a first input coupled to the insertion queue and configured to provide a ring output.
16. The advanced processor of claim 15 , wherein the fast messaging ring component further includes a transmit queue coupled a second input of the multiplexer.
17. The advanced processor of claim 16 , wherein the fast messaging ring component further includes a plurality of receive buffers coupled to the receive queue.
18. The advanced processor of claim 17 , wherein the fast messaging ring component further includes a plurality of associated registers for the plurality of processor cores, the plurality of associated registers including a status register, a memory-mapped configuration register, and a flow control register.