Method and apparatus for implementing cache coherency of a processor
View Patent ↗An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
1. An advanced processor, comprising:
a plurality of processor cores each having a data cache;
a data switch interconnect coupled with the data cache of each of the plurality of processor cores, in which
the data switch interconnect passes information or data among the plurality of processor cores;
means for implementing flow control to manage transmitting data by at least one processor core of the plurality of processor cores based at least in part upon a characteristic of the at least one processor core that performs the action of transmitting the data, wherein the characteristic is used to permit and to stop the at least one processor core from performing the action of transmitting the data and
a level 2 cache coupled to the data switch interconnect which allows sharing of dirty cache lines across the plurality of processor cores, wherein
the data switch interconnect includes a ring arrangement with a plurality of ring elements that are coupled to a respective data cache of the plurality of processor cores and a respective portion of the level 2 cache rather than directly coupled to an instruction cache of at least one of the plurality of processor cores.
2. The advanced processor of claim 1 , wherein the level 2 cache coupled to the data switch interconnect stores information accessible to the plurality of processor cores.
3. The advanced processor of claim 1 , wherein the data switch interconnect is configured to provide one or more data paths to main memory via a first memory bridge and a second memory bridge, both of which are a part of the advanced processor.
4. The advanced processor of claim 1 , wherein the level 2 cache employs a coherency technique based at least in part on a MOSI (Modified, Own, Shared, Invalid) protocol.
5. The advanced processor of claim 1 , further comprising:
a memory bridge coupled to the data switch interconnect and at least one communication port and configured to communicate with the data switch interconnect and the communication port.
6. The advanced processor of claim 1 , further comprising:
a messaging ring component or messaging ring station coupled to the plurality of processor cores.
7. The advanced processor of claim 6 , in which the messaging ring component or messaging ring station is directly coupled to the instruction cache of the at least one of the plurality of processor cores without intervening components.
8. The advanced processor of claim 6 , in which the messaging ring component or messaging ring station is configured to have a data path between a first processor core of the plurality of processor cores and a second processor core of the plurality processor cores.
9. The advanced processor of claim 8 , in which the messaging ring component or messaging ring station is configured such that the data path provides a direct communication between the first processor core and the second processor core without going through a memory element.
10. The advanced processor of claim 9 , in which the first processor core or the second processor core communicates with the memory element by using one or more memory bridges via the messaging ring component or messaging ring station or the data switch interconnect.
11. The advanced processor of claim 1 , in which the characteristic comprises a credit assigned to the at least one of the plurality of processor cores.
12. A method for implementing cache coherency of a processor, comprising:
identifying or determining a plurality of processor cores of the processor, wherein at least one processor core of the plurality of processor cores is configured to include a data cache;
identifying or determining a data switch interconnect of the processor, wherein the action of identifying or determining the data switch interconnect comprises:
coupling the data switch interconnect with the data cache of the at least one processor core, and
configuring the data switch interconnect to pass information or data between at least two of the plurality of the processor cores;
controlling transmitting data by the at least one processor core of the plurality of processor cores by implementing flow control based at least in part upon a characteristic of the at least one processor core, wherein the characteristic is used to permit and to permit and to stop the at least one processor core from performing the action of transmitting the data; and
implementing the cache coherency of the processor by coupling a level 2 cache of the processor to the data switch interconnect to allow sharing of a dirty cache line across the plurality of processor cores of the processor, wherein
the action of implementing the cache coherency comprises coupling a ring arrangement of the data switch interconnect to the data cache of the at least one processor core of the plurality of processor cores rather than directly to an instruction cache of the at least one processor core of the plurality of processor cores.
13. The method for implementing cache coherency of the processor of claim 12 , further comprising:
coupling a messaging ring component or messaging ring station to the plurality of processor cores.
14. The method for implementing cache coherency of the processor of claim 13 , in which the action of coupling the messaging ring component or messaging ring station directly couples the messaging ring component or messaging ring station to the instruction cache of the at least one of the plurality of processor cores without intervening components or modules.
15. The method for implementing cache coherency of the processor of claim 13 , in which the action of coupling the messaging ring component or messaging ring station comprises:
configuring the messaging ring component or messaging ring station to have a data path between a first processor core of the plurality of processor cores and a second processor core of the plurality processor cores.
16. The method for implementing cache coherency of the processor of claim 15 , in which the action of coupling the messaging ring component or messaging ring station further comprises:
configuring the messaging ring component or messaging ring station such that the data path provides a direct communication between the first processor core and the second processor core without going through a memory element.
17. The method for implementing cache coherency of the processor of claim 16 , further comprising:
configuring the processor to cause the first processor core or the second processor core to communicate with the memory element by using one or more memory bridges via the messaging ring component or messaging ring station or the data switch interconnect.
18. A apparatus for implementing cache coherency of a processor, comprising:
a plurality of processor cores of the processor, wherein at least one processor core of the plurality of processor cores is configured to include a data cache;
means for identifying or determining a data switch interconnect of the processor, wherein the means for identifying or determining the data switch interconnect comprises:
means for coupling the data switch interconnect with the data cache of the at least one processor core, and
means for configuring the data switch interconnect to pass information or data between at least two of the plurality of the processor cores;
means for implementing flow control to manage transmitting data by the at least one processor core based at least in part upon a characteristic of the at least one processor core that performs the action of transmitting the data, wherein the characteristic is used to permit and to stop the at least one processor core from performing the action of transmitting the data; and
means for implementing the cache coherency of the processor by coupling a level 2 cache of the processor to the data switch interconnect to allow sharing of a dirty cache line across the plurality of processor cores of the processor, wherein
the means for implementing the cache coherency comprises coupling a ring arrangement of the data switch interconnect to the data cache of the at least one processor core of the plurality of processor cores rather than directly to an instruction cache of the at least one processor core of the plurality of processor cores.
19. The apparatus for implementing cache coherency of the processor of claim 18 , further comprising:
means for coupling a messaging ring component or messaging ring station to the plurality of processor cores.
20. The apparatus for implementing the cache coherency of the processor of claim 19 , in which the means for coupling the messaging ring component or messaging ring station directly couples the messaging ring component or messaging ring station to the instruction cache of the at least one of the plurality of processor cores without intervening components or modules.
21. The method for implementing cache coherency of the processor of claim 18 , in which the means for coupling the messaging ring component or messaging ring station comprises:
means for configuring the messaging ring component or messaging ring station to have a data path between a first processor core of the plurality of processor cores and a second processor core of the plurality processor cores; and
configuring the messaging ring component or messaging ring station such that the data path provides a direct communication between the first processor core and the second processor core without going through a memory element.