IP Library Granted Patent US 7,613,201
Granted Patent B1
US 7,613,201 · App. 10/826,215 · Granted Nov 3, 2009

Stacked network switch using resilient packet ring communication protocol

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Quick Facts
Patent No.
US 7,613,201
App. No.
10/826,215
Granted
Nov 3, 2009
Kind
B1
Abstract

A stacked switch using a resilient packet ring protocol comprises a plurality of switch modules coupled to one another in a ring topology and each having a plurality of external terminals for interfacing with external devices. Each switch module includes an external interface for communicating with the external terminals, the external interface configured to communicate using a communication protocol; and an internal interface for communicating with other switches, the internal interface using a resilient packet ring (RPR) protocol. Advantages of the invention include the ability to flexibly create a high performance stacked switch with advanced features.

Claims (34)

1. A stacked switch using a resilient packet ring protocol comprising:

a plurality of switch modules coupled to one another in a ring topology and each having a plurality of external terminals for interfacing with external devices, where each switch module includes:

an external interface for communicating with the external terminals, the external interface configured to communicate using a communication protocol; and

an internal interface for communicating with other switches, the internal interface using a resilient packet ring (RPR) protocol;

a master management processor coupled to one or more of the switch modules and configured to provide instructions regarding communication of information between each switches' external interface and internal interface, and to control data flow; and

a slave management processor coupled to the master management processor through at least one switch and one or more of the switch modules and configured to provide the instructions regarding the communication of information between each switches' external interface and internal interface, and to control the data flow;

wherein statistics associated with a communication of data through at least one of the switch modules are stored;

wherein the statistics are evaluated to generate a link signal representative of desired links/ports to be aggregated; and

wherein a link aggregation port is selectively aggregated to respond to the link signal and to dynamically set one or more switch modules' external terminals to selectively aggregate information to and from the switch modules;

wherein marker information is selectively introduced into the data to ensure that the integrity of the data is reasonably maintained when a link aggregation is modified.

2. The stacked switch of claim 1 , wherein each switch module further includes:

a controller coupled to the external interface and the internal interface and configured to selectively communicate information between the external interface and the internal interface.

3. The stacked switch of claim 2 wherein:

the master management processor is configured to assign a master/slave relationship based on predetermined criteria; and

the slave management processor is configured to become another master management processor if the master management processor fails.

4. The stacked switch of claim 2 , wherein:

the link aggregation port is coupled to one or more switch modules' external terminals and configured to selectively aggregate the information to and from the switch modules.

5. The stacked switch of claim 4 , further comprising:

a memory configured to store the statistics associated with the communication of data through the at least one switch module;

wherein the master management processor is configured to evaluate the statistics in the memory and to generate the link signal representative of the desired links/ports to be aggregated.

6. The stacked switch of claim 5 , wherein:

the master management processor is configured to introduce the marker information into the data to ensure that the integrity of the data is reasonably maintained when the link aggregation is modified.

7. A method of switching data through a stacked switch using a resilient packet ring protocol, the stacked switch having a plurality of modules, where each module includes an external interface for communicating with external terminals and an internal interface for communicating with other switches using a resilient packet ring (RPR) protocol, comprising:

storing statistics associated with a communication of data through at least one module in a switch;

evaluating the statistics to generate a link signal representative of desired links/ports to be aggregated;

selectively activating a link aggregation port to respond to the link signal and to dynamically set one or more switch modules' external terminals to selectively aggregate information to and from the switch modules; and

selectively introducing marker information into the data to ensure that the integrity of the data is reasonably maintained when a link aggregation is modified;

wherein a master management processor is coupled to one or more of the switch modules and configured to provide instructions regarding communication of information between each switches' external interface and internal interface, and to control data flow; and

wherein a slave management processor is coupled to the master management processor through at least one switch and one or more of the switch modules and configured to provide the instructions regarding the communication of information between each switches' external interface and internal interface, and to control the data flow.

8. The method of claim 7 , wherein the statistics are based on port traffic.

9. The method of claim 8 , wherein the statistics are used for load-balancing purposes.

10. The method of claim 7 , further comprising sending a marker to facilitate handover from a first port to a second port.

11. The method of claim 10 , wherein a marker technique is employed to prevent an out-of-order problem when handing over traffic from the first port to the second port.

12. The method of claim 7 , wherein local ports on the switch are aggregated.

Assignments (10)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: NETLOGIC I LLC
To: BROADCOM CORPORATION
Reel/Frame 035443/0763 →
CHANGE OF NAME Recorded Apr 16, 2015
From: NETLOGIC MICROSYSTEMS, INC.
To: NETLOGIC I LLC
Reel/Frame 035443/0824 →
RELEASE OF SECURITY INTEREST Recorded Sep 2, 2011
From: VENTURE LENDING & LEASING, INC
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 026855/0108 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2010
From: RMI CORPORATION
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 023926/0338 →
CHANGE OF NAME Recorded May 1, 2008
From: RAZA MICROELECTRONICS, INC.
To: RMI CORPORATION
Reel/Frame 020886/0454 →
SECURITY INTEREST Recorded Apr 24, 2007
From: RAZA MICROELECTRONICS, INC.
To: VENTURE LENDING & LEASING IV, INC.
Reel/Frame 019224/0254 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2004
From: YANG, BRIAN HANG WAI; HO, KEN K.; LATIF, AAMER
To: RAZA MICROELECTRONICS, INC.
Reel/Frame 015231/0623 →