IP Library Granted Patent US 6,972,494
Granted Patent B1
US 6,972,494 · App. 09/639,288 · Granted Dec 6, 2005

Integrated circuit die for wire bonding and flip-chip mounting

Assignee: Agere Systems Inc.
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Quick Facts
Patent No.
US 6,972,494
App. No.
09/639,288
Granted
Dec 6, 2005
Kind
B1
Abstract

An integrated circuit die carries conductive pads and thereon, the larger pads being suitable for flip-chip assembly and the smaller pads being suitable for wire bond assembly. The pitch between pads is at least the minimum required for flip-chip assembly, whereas the pitch between each of pads and the adjacent pad or pads is at least the minimum required for wire bond assembly. For wire bond assembly a passivation layer exposing all pads is provided, whereas for flip-chip assembly a passivation layer exposes only certain pads so that conductive bumps may be provided. The provision of pads complying with the minimum spacing requirements for both flip-chip and wire bond assembly enables a “dual purpose” (e.g. one set of pads being for normal production and another set for testing purposes) die to be produced without any increase in die size.

Claims (7)

1. An integrated circuit die including first and second sets of conductive pads for enabling external connections to be made to the integrated circuit, there being at least a first predetermined center-to-center spacing between each pad of the first set and the adjacent pad or pads of the first set, and at least a second predetermined center-to-center spacing, less than said first spacing, between each pad of the second set and the adjacent pad or pads of the first and second sets, wherein the pads of the first set are disposed in two lines adjacent one or more edges of the die, the pads of the first set in one of the two lines being disposed in staggered relationship with respect to the pads of the first set in the other of the two lines, and a passivation layer exposing only pads of the first set, or exposing pads of the first and second sets.

2. A die as claimed in claim 1 wherein the pads of the second set are disposed in one of the two lines.

3. A die as claimed in claim 1 wherein the pads of the first set are larger in area than the pads of the second set.

4. A die as claimed in claim 3 wherein the area of each pad of the first set and the first predetermined center-to-center spacing are suitable for flip-chip assembly of the die, and the area of each pad of the second set and the second predetermined center-to-center spacing are suitable for wire bond assembly of the die.

5. A die as claimed in claim 1 wherein the pads of the second set are disposed in line adjacent one or more edges of the die.

6. A die as claimed in claim 1 wherein the pads of the second set are disposed in one of the two lines.

7. A die as claimed in any preceding claim wherein the first set of pads is connected to one set of connection points in the integrated circuit, and the second set of pads is connected to another set of connection points in the integrated circuit.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
MERGER Recorded Feb 20, 2015
From: AGERE SYSTEMS GUARDIAN CORP.
To: AGERE SYSTEMS INC.
Reel/Frame 035058/0884 →
MERGER Recorded Feb 20, 2015
From: AGERE SYSTEMS INC.
To: AGERE SYSTEMS LLC
Reel/Frame 035058/0895 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035059/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2002
From: ADDINALL, ROSS; DAVIES, GARETH R.
To: AGERE SYSTEMS GUARDIAN CORPORATION
Reel/Frame 012722/0926 →
Priority Claims (2)
EP 99306444 · Aug 17, 1999 · regional
EP 99309842 · Dec 7, 1999 · regional