Dual spacer process for non-volatile memory devices
View Patent ↗In a two-step spacer fabrication process for a non-volatile memory device, a thin oxide layer is deposited on a wafer substrate leaving a gap in the core of the non-volatile memory device. Implantation and/or oxide-nitride-oxide removal can be accomplished through this gap. After implantation, a second spacer is deposited. After the second spacer deposition, a periphery spacer etch is performed. By the above method, a spacer is formed.
1. A method for forming a spacer, comprising:
depositing a first oxide layer over at least two adjacent polysilicon lines in each of a core area and a periphery area;
performing a first spacer etch in the core area and the periphery area;
implanting an area located between at least two adjacent polysilicon lines in the core area;
applying a second oxide layer over the core area and the periphery area; and
performing a second spacer etch over the periphery area, the core area retaining an amount of the second oxide between the adjacent polysilicon lines while the periphery area is deplete of the second oxide between its adjacent polysilicon lines.
2. The method of claim 1 wherein the first oxide layer has a thickness of less than one-half the distance between adjacent polysilicon lines.
3. The method of claim 1 , further comprising implanting an area located between at least two adjacent polysilicon lines in the periphery area.
4. The method of claim 3 , the implanting of the area located between at least two polysilicon lines in the periphery area occurring subsequent to performing the first spacer etch.
5. The method of claim 1 , the implanting of the area located between at least two adjacent polysilicon lines occurs after application of the second spacer etch.
6. The method of claim 1 , prior to performing the second spacer etch depositing resist over the periphery area.
7. The method of claim 1 , prior to implanting an area between at least two adjacent polysilicon lines masking the core area and the periphery area.
8. A process for fabricating a non-volatile memory device comprising:
providing a substrate having a core are, a periphery area, and at least two adjacent polysilicon lines in each of the core area and the periphery area;
depositing a first oxide layer over the adjacent polysilicon lines, the first oxide layer has a thickness of less than one-half the distance between adjacent polysilicon lines;
performing a first spacer etch in the core area and the periphery area;
implanting an area located between at least two adjacent polysilicon lines in the core area;
depositing a second oxide layer over the core area and the periphery area; and
performing a second spacer etch over the periphery area.
9. The process of claim 8 , further comprising performing a second spacer etch over the core area.
10. The process of claim 8 , the implanting of an area occurs after the performing of the first spacer etch.
11. The process of claim 8 , further comprising implanting an area located between at least two polysilicon lines in the periphery area.
12. The process of claim 11 , the implanting of an area located between at least two polysilicon lines in the periphery area occurs after the performing of the first spacer etch.
13. The process of claim 11 , the implanting of an area located between at least two polysilicon lines in the core area occurs after the performing of the second spacer etch.
14. The process of claim 8 , the substrate is a silicon wafer.
15. The process of claim 8 , the depositing of the first oxide layer comprising passing nitrogen dioxide gas over the substrate.
16. The process of claim 8 , farther comprising depositing a nitride layer between the first oxide layer and the second oxide layer.
17. The process of claim 16 , the depositing of the nitride layer comprising passing a gas composed of at least silicon, hydrogen and ammonia.
18. The process of claim 8 , the depositing of the first oxide layer partially fills an interstitial gap between adjacent polysilicon lines.
19. The process of claim 8 , the core area retaining an amount of the second oxide between adjacent polysilicon lines while the periphery area is deplete of the second oxide between its adjacent polysilicon lines.