High speed physical circuits of memory interface
View Patent ↗A memory interface for a switching router in a network communications system. The interface operates at 200 MHz PLL clock using high speed transistor logic I/O buffers. The interface allows transfer of clock synchronization signals along with the data signals. This allows the setup/hold times to be optimized for an inbound or outbound data pipeline. During writes, data is at least driven one clock cycle after the address. The interface provides flexibility by utilizing at least two clock cycles in order to accommodate a myriad of memory devices (e.g., burst mode SSRAMs having HSTL I/O). In operation, most of the data transfers through the interface are either direct reads or lookup reads. The interface stores writes are stored in a buffer in order to reduce bus turn around penalties.
1. An interface for transferring data between a network switching router for fast path processing of network data packets and at least one memory device, comprising:
an external portion having a clock source for generating a continuous cyclic signal, a clock buffer coupled to said clock source for registering said continuous cyclic signal and providing a plurality of timing control signals and said at least one memory device; and
an internal portion having an input cell, a phase locked loop, at least one multiplexer, and a plurality of controlled latches, said input cell is coupled to said clock buffer for receiving one of said timing control signals and transforming said timing control signals into pulses, said phase locked loop coupled to said input cell for receiving said pulses, said phase locked loop maintaining a timing pulse frequency in response to said pulses, said at least one multiplexer configured to gate data transfer to and from said internal portion and said external portion, said controlled latches responsive to said timing pulse frequency for coupling said switching router to said at least one multiplexer, such that said switching router stores and retrieves data to and from said at least one memory device at a rate about 10 gigabits per second,
wherein said at least one memory receives another one of said timing control signals from said clock buffer; and
wherein said timing pulse frequency provides synchronization between said external portion and said internal portion.
2. The interface according to claim 1 , wherein the phase locked loop includes a feedback delay for adjusting said timing pulse frequency, wherein said timing pulse frequency is maintained at a fixed rate.
3. The interface according to claim 1 , wherein a first portion of said plurality of controlled latches is configured to receive data and control signals from said switching router for storing in said memory device, said first portion of controlled latches is controlled by said timing pulse frequency.
4. The interface according to claim 3 , wherein a second portion of said plurality of controlled latches is configured to receive data from said memory device for retrieval by said switching router, said second portion of controlled latches is controlled by said timing pulse frequency.
5. The interface according to claim 3 , wherein a third portion of said plurality of controlled latches is configured to synchronize data received from said first portion of controlled latches for verifying a skew rate of data transfer from said switching router to said multiplexer, said third portion of controlled latches is controlled by said pulses of said input cell.
6. The interface according to claim 1 , wherein said clock being an oscillator having a frequency of at least 200 MHz.
7. The interface according to claim 1 , wherein said at least one memory device includes at least a first bank and a second bank of SRAM.
8. The interface according to claim 7 , wherein said first bank and said second bank of SRAM each being synchronous SRAM.
9. The interface according to claim 1 , further comprising a plurality of delay units for preventing data transfer conflicts.
10. The interface according to claim 1 , wherein said multiplexer and said memory device having I/O cells coupled therebetween for buffering the data to and from said memory device.