IP Library Granted Patent US 7,202,171
Granted Patent B2
US 7,202,171 · App. 09/752,685 · Granted Apr 10, 2007

Method for forming a contact opening in a semiconductor device

Assignee: Micron Technology, Inc.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,202,171
App. No.
09/752,685
Granted
Apr 10, 2007
Kind
B2
Abstract

A method of forming a self-aligned contact opening in an insulative layer formed over a substrate in a semiconductor device involves etching the insulative layer with at least one fluorocarbon and ammonia.

Claims (24)

1. A process for forming an opening in an insulative layer formed over a substrate in a semiconductor device, said process comprising:

forming a pair of adjacent gate stacks over said substrate;

forming sidewall spacers on sidewalls of said adjacent gate stacks;

forming an insulative layer over said substrate;

forming a patterned photoresist mask layer over said insulative layer; and,

etching an opening in said insulative layer defined at least in part by said sidewall spacers through an aperture in said patterned photoresist mask layer, wherein said opening is etched through to said substrate using a combination consisting essentially of ammonia and at least one fluorocarbon, wherein said at least one fluorocarbon is selected from the group consisting of C 4 F 8 , C 4 F 6 , C 5 F 8 , CF 4 , C 2 F 6 , CHF 3 , CH 2 F 2 and C 3 F 8 , and wherein the flow rate ratio of said at least one fluorocarbon to said ammonia is from about 2:1 to about 40:1, and wherein the step of etching an opening in said insulative layer forms a protective layer on said sidewall spacers that is from about 5 to about 50 Å thick.

2. The method of claim 1 , wherein said etching is performed to produce a self-aligned contact opening in said insulative layer, said opening is self-aligned between said adjacent gate stack structures with sidewall spacers.

3. The process of claim 1 , wherein said etching is performed in a reaction chamber.

4. The process of claim 3 , wherein said at least one fluorocarbon and said ammonia are flowed into said reaction chamber such the flow rate ratio of said at least one fluorocarbon to said ammonia is not less than about 3:1.

5. The process of claim 1 , wherein said flow rate ratio is within the range of about 4:1 to about 10:1.

6. The process of claim 1 , wherein said etching is performed without forming an etch stop.

7. The process of claim 6 , wherein said opening is formed between said sidewall spacers on said pair of adjacent gate stacks.

8. The process of claim 7 , wherein said etching is performed at a temperature within the range of about −50 to about 80 degrees Celsius.

9. The process of claim 8 , wherein said etching is performed at a temperature within the range of about 0 to about 80 degrees Celsius.

10. The process of claim 9 , wherein said method further comprises removing said photoresist mask layer after said etching.

11. A method of forming a conductive plug between adjacent gate stacks with sidewall spacers and inside a self-aligned contact opening formed in an insulative layer provided over a substrate in a semiconductor device, said method comprising:

contacting said insulative layer with a plasma etchant mixture consisting essentially of ammonia and at least one fluorocarbon at a temperature within the range of from about −50 to about 80 degrees Celsius so as to form a self-aligned contact opening defined at least in part by said sidewall spacers on adjacent gate stacks in said insulative layer without an etch stop, wherein said contacting further forms a protective layer over opposed sidewall spacers which have been formed over said adjacent gate stacks that is from about 5 to about 50 Å thick, wherein the flow rate ratio of said at least one flurocarbon to said ammonia is from about 2:1 to about 40:1, and said flow rate of said ammonia is at least about 2 sccm; and,

depositing a conductive plug inside said etched opening such that said conductive plug is separated from said sidewall spacers by said protective layer.

12. The method of claim 11 , wherein said contacting is performed by flowing said ammonia over said device in a reaction chamber at a flow rate within the range of about 2 sccm to about 6 sccm.

13. The method of claim 11 , wherein said at least one fluorocarbon is at least one member selected from the group consisting of C 4 F 8 , C 4 F 6 , C 5 F 8 , CF 4 , CHF 3 , and CH 2 F 2 and is flowed over said device at a flow rate within the range of about 10 sccm to about 45 sccm.

14. The method of claim 13 , wherein said mixture comprises at least two fluorocarbons and said flow rate ratio of each said fluorocarbon to said ammonia is within the range of about 3:1 to about 20:1.

15. The method of claim 14 , wherein said mixture comprises three fluorocarbons and said flow rate ratio is within the range of about 4:1 to about 10:1.

16. The method of claim 11 , wherein said protective layer is a nitrogen containing layer.

17. The method of claim 11 , wherein said temperature is a pedestal temperature and said range is from about 0 to about 50 degrees Celsius.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2001
From: TRAPP, SHANE J.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 011420/0770 →
Continuity (1)
Related Publication 20020123226A1 · Sep 5, 2002