Granted Patent
Utility
US 6,782,498
· Confirmation No. 8270
SEMICONDUCTOR MEMORY DEVICE ALLOWING MOUNTING OF BUILT-IN SELF TEST CIRCUIT WITHOUT ADDITION OF INTERFACE SPECIFICATION
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2004-07-20 | IFEE |
Issue Fee Payment (PTO-85B) | 1 | View | |
| 2001-01-11 | TRNA |
Transmittal of New Application | 1 | View | |
| 2001-01-11 | SPEC |
Specification | 22 | View | |
| 2001-01-11 | CLM |
Claims | 7 | View | |
| 2001-01-11 | ABST |
Abstract | 1 | View | |
| 2001-01-11 | DRW |
Drawings-only black and white line drawings | 8 | View |
Inventors
Tetsushi Tanizaki
Hyogo, JAPAN
Takeshi Hamamoto
Hyogo, JAPAN
Attorneys & Agents of Record
Classification
USPC
714/733
Prosecution
- Examiner
- TORRES, JOSEPH D
- Art Unit
- 2133
- Docket No.
- 49657-943
- Confirmation No.
- 8270
Foreign Priority
2000-004881(P)
·
2000-01-13
·
JAPAN
Publication
- Pub. No.
- US20010054164A1
- Pub. Date
- 2001-12-20
Patent Term Adjustment
0days
No related applications found.
CHANGE OF ADDRESS
Recorded 2017-11-29
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2004-04-07
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2003-09-10
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2001-03-27
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Quick Facts
- Patent No.
- US 6,782,498
- App. No.
- 09/758,042
- Filed
- 2001-01-11
- Granted
- 2004-08-24
- Pub. No.
- US20010054164A1
- Examiner
- TORRES, JOSEPH D
- Art Unit
- 2133
- PTA
- 0 days
External Links