Patent Application
Utility
App. No. 09/766,206
· Confirmation No. 8761
METHOD FOR FORMING A SHALLOW TRENCH ISOLATION STRUCTURE IN A SEMICONDUCTOR DEVICE
Inventor:
Kiyotaka Miwa
Patent Expired Due to NonPayment of Maintenance Fees Under 37 CFR 1.362
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-01-19 | TRNA |
Transmittal of New Application | 1 | View | |
| 2001-01-19 | SPEC |
Specification | 27 | View | |
| 2001-01-19 | CLM |
Claims | 6 | View | |
| 2001-01-19 | ABST |
Abstract | 1 | View | |
| 2001-01-19 | DRW |
Drawings-only black and white line drawings | 7 | View | |
| 2001-01-19 | OATH |
Oath or Declaration filed | 1 | View |
Inventors
Kiyotaka Miwa
Tokyo, JAPAN
Attorneys & Agents of Record
Classification
USPC
438/692
H10W10/014
H10W10/17
Prosecution
- Examiner
- POWELL, WILLIAM A
- Art Unit
- 1765
- Customer No.
- 26339
- Docket No.
- KOM-02501
- Confirmation No.
- 8761
Foreign Priority
2000-013430
·
2000-01-21
·
JAPAN
Publication
- Pub. No.
- US20010009809A1
- Pub. Date
- 2001-07-26
Patent Term Adjustment
-107days
No related applications found.
from
NEC CORPORATION
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2003-02-25
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Quick Facts
- App. No.
- 09/766,206
- Filed
- 2001-01-19
- Granted
- 2002-08-06
- Pub. No.
- US20010009809A1
- Examiner
- POWELL, WILLIAM A
- Art Unit
- 1765
- PTA
- -107 days
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