IP Library Granted Patent US 6,335,875
Granted Patent Utility
US 6,335,875 · Confirmation No. 4725

Memory circuit/logic circuit integrated device capable of reducing term of works

Inventor: Tsukasa Ooishi
⬇ PDF
Code Description Pages PDF
2001-03-22 DRW Drawings-only black and white line drawings 6 View
2001-01-26 TRNA Transmittal of New Application 3 View
2001-01-26 SPEC Specification 55 View
2001-01-26 CLM Claims 8 View
2001-01-26 ABST Abstract 1 View
2001-01-26 DRW Drawings-only black and white line drawings 53 View
2001-01-26 OATH Oath or Declaration filed 3 View
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Quick Facts
Patent No.
US 6,335,875
App. No.
09/769,390
Filed
2001-01-26
Granted
2002-01-01
Pub. No.
US20010012231A1
Art Unit
2824
PTA
-49 days