IP Library › Granted Patent US 6,275,424
Granted Patent Utility
US 6,275,424 · Confirmation No. 4458

Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device

Patented Case View Patent ↗
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 Code Description Pages PDF
2001-01-31 TRNA Transmittal of New Application 6 View
2001-01-31 SPEC Specification 10 View
2001-01-31 CLM Claims 4 View
2001-01-31 ABST Abstract 1 View
2001-01-31 DRW Drawings-only black and white line drawings 3 View
2001-01-31 OATH Oath or Declaration filed 3 View
2001-01-31 TRNA Transmittal of New Application 6 View
2001-01-31 SPEC Specification 10 View
2001-01-31 CLM Claims 4 View
2001-01-31 ABST Abstract 1 View
2001-01-31 DRW Drawings-only black and white line drawings 3 View
2001-01-31 OATH Oath or Declaration filed 3 View
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Quick Facts
Patent No.
US 6,275,424
App. No.
09/774,509
Filed
2001-01-31
Granted
2001-08-14
Examiner
DINH, SON T
Art Unit
2824
PTA
0 days