Differential receiver architecture
View Patent ↗A receiver circuit for a tester for electronic devices is provided. The receiver circuit includes a clock receiver that is adapted to receive a source synchronous clock signal from a device under test. The receiver circuit further includes a data receiver that is responsive to the clock circuit. The data receiver is adapted to receive at least one differential data signal from the device under test. The receiver circuit also includes a trigger receiver that is responsive to the clock circuit. The trigger receiver is adapted to receive a trigger signal from the device under test. Finally, the receiver circuit includes a control circuit that is coupled to the trigger receiver. The control circuit is adapted to generate a start alignment capture signal based on the received trigger signal to initiate capture of data received at the data receiver for comparison with expected values.
1. A channel card for a tester for electronic devices, the channel card comprising:
a clock receiver that is adapted to receive a source synchronous clock signal from a device under test;
a data receiver, responsive to the clock circuit, the data receiver adapted to receive at least one differential data signal from the device under test;
a trigger receiver, responsive to the clock circuit, the trigger receiver adapted to receive a trigger signal from the device under test;
a control circuit, coupled to the trigger receiver, the control circuit adapted to generate a start alignment capture signal based on the received trigger signal; and
a data capture circuit, responsive to the data receiver and the control circuit, the data capture circuit adapted to initiate capturing of data from the data receiver based on the capture signal.
2. The channel card of claim 1 , wherein the data capture circuit comprises:
at least one serial to parallel converter, responsive to the data receiver; and
a memory circuit, responsive to the at least one serial to parallel converter, wherein the serial to parallel converter begins providing parallel data to the memory circuit based on the capture signal.
3. The channel card of claim 1 , wherein the data capture circuit comprises a comparison circuit that compares the captured data with expected values.
4. The channel card of claim 1 , wherein the clock receiver comprises first and second verniers that selectively adjust the leading edge and trailing edge of the clock signal.
5. The channel card of claim 1 , wherein the data receiver comprises a data receiver that receives data on both a leading edge and a trailing edge of a clock pulse.
6. The channel card of claim 1 , wherein the data receiver comprises:
a differential receiver adapted to receive a differential data signal from the device under test;
a fan out circuit, responsive to the differential receiver; and
first and second flip-flops, responsive to the fan out circuit and the clock receiver, wherein the first flip-flop captures data on a leading edge of the clock signal and the second flip-flop captures data on a trailing edge of the clock signal.
7. The channel card of claim 1 , wherein the trigger receiver comprises a logic circuit that selects one of a plurality of trigger modes.
8. The channel card of claim 1 , wherein the trigger receiver comprises a logic circuit that selects among leading edge, trailing edge, or next edge as a trigger signal.
9. A method for testing an electric device having differential signal outputs, the method comprising:
receiving a differential clock pair from a device under test;
receiving a differential data signal from at least one of the differential signal outputs of the device under test;
receiving a differential trigger signal from the device under test;
latching the trigger signal based on the differential clock pair;
when the trigger signal is received, initiating the capture of the differential data the based on the trigger signal and the differential clock pair.
10. The method of claim 9 , wherein receiving a trigger signal comprises receiving one of a control or a frame signal.
11. The method of claim 9 , wherein receiving a differential data signal comprises receiving a double data rate (DDR) differential data signal.
12. The method of claim 9 , wherein initiating capture of the differential data comprises initiating the operation of at least one serial to parallel converter for storing the data in a memory.
13. The method of claim 9 , wherein initiating capture of the differential data comprises latching the data using the differential clock pair and the trigger signal and comparing the latched data with expected values.
14. The method of claim 9 , and further comprising generating at least one control signal based on the at least one trigger signal.
15. A tester for electronic devices, the tester comprising:
a device interface board having a receptacle that is adapted to receive a device under test;
a computer that is programmed to provide test data to the device under test and to process signals received from the device under test;
a test head, coupled between the device interface board and the computer, the test head including at least one channel card; and
the at least one channel card including:
a clock receiver that is adapted to receive a source synchronous clock signal from the device under test,
a data receiver, responsive to the clock circuit, the data receiver adapted to receive at least one differential data signal from the device under test;
a trigger receiver, responsive to the clock circuit, the trigger receiver adapted to receive a trigger signal from the device under test;
a control circuit, coupled to the trigger receiver, the control circuit adapted to generate a capture signal based on the received trigger signal; and
a data capture circuit, responsive to the data receiver and the control circuit, the data capture circuit adapted to initiate capturing of data from the data receiver based on the capture signal.
16. The tester of claim 15 , wherein the data capture circuit comprises:
at least one serial to parallel converter, responsive to the data receiver; and
a memory circuit, responsive to the at least one serial to parallel converter, wherein the serial to parallel converter begins providing parallel data to the memory circuit based on the capture signal.
17. The tester of claim 15 , wherein the data capture circuit comprises a comparison circuit that compares the captured data with expected values.
18. The tester of claim 15 , wherein the clock receiver comprises first and second verniers that selectively adjust the leading edge and trailing edge of the clock signal.
19. The tester of claim 15 , wherein the data receiver comprises a data receiver that receives data on both a leading edge and a trailing edge of a clock pulse.
20. The tester of claim 15 , wherein the data receiver comprises:
a differential receiver adapted to receive a differential data signal from the device under test;
a fan out circuit, responsive to the differential receiver; and
first and second flip-flops, responsive to the fan out circuit and the clock receiver, wherein the first flip-flop captures data on a leading edge of the clock signal and the second flip-flop captures data on a trailing edge of the clock signal.
21. The tester of claim 15 , wherein the trigger receiver comprises a logic circuit that selects one of a plurality of trigger modes.
22. The tester of claim 15 , wherein the trigger receiver comprises a logic circuit that selects among leading edge, trailing edge, or next edge as a trigger signal.
23. A receiver circuit for a tester for electronic devices, the receiver circuit comprising:
a clock receiver that is adapted to receive a source synchronous clock signal from a device under test;
a data receiver, responsive to the clock circuit, the data receiver adapted to receive at least one differential data signal from the device under test;
a trigger receiver, responsive to the clock circuit, the trigger receiver adapted to receive a trigger signal from the device under test; and
a control circuit, coupled to the trigger receiver, the control circuit adapted to generate a capture signal based on the received trigger signal to initiate capture of data received at the data receiver for comparison with expected values.