Granted Patent
Utility
US 6,665,203
· Confirmation No. 5539
A SEMICONDUCTOR MEMORY DEVICE HAVING A HIERARCHIAL I/O STRUCTURE
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2003-10-22 | IFEE |
Issue Fee Payment (PTO-85B) | 1 | View | |
| 2001-05-30 | TRNA |
Transmittal of New Application | 2 | View | |
| 2001-05-30 | SPEC |
Specification | 78 | View | |
| 2001-05-30 | CLM |
Claims | 12 | View | |
| 2001-05-30 | ABST |
Abstract | 1 | View | |
| 2001-05-30 | DRW |
Drawings-only black and white line drawings | 15 | View | |
| 2001-05-30 | OATH |
Oath or Declaration filed | 4 | View |
Inventors
Attorneys & Agents of Record
Classification
USPC
365/51
Prosecution
- Examiner
- PHUNG, ANH K
- Art Unit
- 2824
- Customer No.
- 20457
- Docket No.
- 501.40141X00
- Confirmation No.
- 5539
Foreign Priority
2000-196024
·
2000-06-29
·
JAPAN
Publication
- Pub. No.
- US20020001215A1
- Pub. Date
- 2002-01-03
Patent Term Adjustment
-34days
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2018-08-21
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2006-12-08
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2001-05-30
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Quick Facts
- Patent No.
- US 6,665,203
- App. No.
- 09/866,623
- Filed
- 2001-05-30
- Granted
- 2003-12-16
- Pub. No.
- US20020001215A1
- Examiner
- PHUNG, ANH K
- Art Unit
- 2824
- PTA
- -34 days
External Links