Delay time estimation method and recording medium storing estimation program
View Patent ↗The operating characteristic of a transistor, modeled by a resistive element having fixed resistance and a power source voltage that varies with time, is segmented into a linearity region in which a current increases as a gate potential varies and a saturation region in which the current gradually decreases as the gate potential remains at a constant level, so that gradual decrease in current in a saturation region of the transistor is properly reflected and a delay time is estimated in a precise manner.
1. A delay time estimation method for estimating a delay time in a logic circuit that includes a MOS transistor
said method comprising the steps of:
constructing a delay library including function information for specifying a model of an Ids-Vds characteristic at a given gate potential and also including function information related to a slew rate specifying a fixed delay, where Ids denotes a drain-source current and Vds denotes a drain-source voltage;
modeling the MOS transistor by a resistive element having fixed resistance and a power source voltage that varies with time;
determining an operating current characteristic of the MOS transistor thus modeled and segmenting the operating current characteristic based upon the delay library into a first region in which a current increases as a gate potential varies, a second region corresponding to a saturation region of the MOS transistor in which region the current gradually decreases as the gate potential remains constant, and a third region corresponding to a linearity region of the MOS transistor in which region the current decreases as the gate potential remains constant; and
storing the determined estimated delay time of the MOS transistor and output thereof.
2. The delay time estimation method according to claim 1 , wherein said logic circuit is constructed by a plurality of cells each including a MOS transistor, wherein the delay estimation is executed to the cell at the last stage of said logic circuit.
3. The delay time estimation method according to claim 1 , wherein
E=Rs×i ( t )+ v ( t )
holds for t=Δt 1 and t=Δt 1 +Δt 2 , where E denotes the power source voltage, Rs denotes resistance of a model of the power source, i(t) denotes a charge current of a load model, v(t) denotes a charge voltage of the load model, and wherein
V 1 , Δt 1 and Δt 2 are determined based on a fact that values of E−v(t) and i(t) reside on an Ids-Vds characteristic curve at a given gate potential, where Ids denotes a drain-source current and Vds denotes a drain-source voltage, and where
V 1 denotes a voltage at a boundary between the first region and the second region, Δt 1 denotes a time required to arrive at the boundary, and Δt 2 denotes time required to reach the power source voltage via the second region.
4. A recording medium storing a computer program that allows a computer to perform the delay time computation method according to claim 1 .
5. The delay time estimation method according to claim 2 , further comprising the step of determining an input slew rate of a waveform input in said cell at the last stage and an internal delay of said logic circuit based on an input slew rate of a waveform input in said logic circuit and a delay parameter extracted for said logic circuit.