Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics
View Patent ↗A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.
1. In a memory array having at least two memory planes of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, each respective memory cell within a memory plane coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines associated with the memory plane, a method of sensing the data state of one or more selected memory cells comprising the steps of:
biasing the X-lines and Y-lines so that a forward bias voltage of at least about 1 volt is impressed across one or more selected memory cells, and further so that no appreciable bias voltage is impressed across at least a first group of half-selected memory cells; and
sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell, to determine the data state of each selected memory cell;
wherein each of the first group of half-selected memory cells is coupled to a selected X-line or Y-line whose current flow is sensed; and
wherein the memory cells comprise an amorphous solid.
2. The method of claim 1 wherein the memory cells comprise:
antifuse memory cells having a programming voltage in the range of about 5–20 volts.
3. The method of claim 1 wherein the memory cells comprise:
fuse memory cells having a programming voltage in the range of about 5–20 volts.
4. The method of claim 1 further comprising:
biasing the X-lines and Y-lines so that no appreciable bias voltage is impressed across a second group of half-selected memory cells;
wherein each of the second group of half-selected memory cells is not coupled to a selected X-line or Y-line whose current flow is sensed.
5. The method of claim 1 further comprising:
biasing the X-lines and Y-lines so that no appreciable bias voltage is impressed across any half-selected memory cells.
6. The method of claim 1 wherein the sensing step comprises:
sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell while keeping any such current-sensed X-line or Y-line substantially unchanged in voltage.
7. The method of claim 1 wherein:
the X-lines are always connected to a respective anode terminal of associated memory cells.
8. The method of claim 1 wherein:
the X-lines are always connected to a respective cathode terminal of associated memory cells.
9. The method of claim 7 wherein:
a selected X-line is either driven or sensed and the selected Y-line either sensed or driven, irrespective of which memory cell is selected.
10. The method of claim 1 wherein the memory cells comprise a semiconductor material.
11. The method of claim 1 wherein the memory cells comprise an organic polymer.
12. The method of claim 1 wherein the memory cells comprise a phase change material.
13. The method of claim 1 wherein:
the memory cells comprise antifuse memory cells.
14. The method of claim 1 wherein the sensed current flowing on the at least one of the respective X-line or respective Y-line associated with each selected memory cell flows outward from the memory array toward a sense circuit.
15. The method of claim 6 wherein the sensed current flowing on the at least one of the respective X-line or respective Y-line associated with each selected memory cell flows outward from the memory array toward a sense circuit.
16. In a memory array having at least two memory planes of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, each respective memory cell within a memory plane coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines associated with the memory plane, a method of sensing the data state of one or more selected memory cells comprising the steps of:
biasing the X-lines and Y-lines so that a forward bias voltage of at least about 1 volt is impressed across one or more selected memory cells, and further so that no appreciable bias voltage is impressed across at least a first group of half-selected memory cells; and
sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell, to determine the data state of each selected memory cell;
wherein each of the first group of half-selected memory cells is coupled to a selected X-line or Y-line whose current flow is sensed; and
wherein the X-lines are connected to respective anode terminals of some associated memory cells, and to respective cathode terminals of other associated memory cells.
17. The method of claim 16 wherein:
a selected X-line is either driven or sensed depending upon whether it connects to a respective anode terminal or a respective cathode terminal of a selected memory cell.
18. An integrated circuit comprising:
a memory array having at least two memory planes of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, each respective memory cell within a memory plane coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines associated with the memory plane;
means for biasing the X-lines and Y-lines so that a forward bias voltage of at least about 1 volt is impressed across one or more selected memory cells, and further so that no appreciable bias voltage is impressed across at least a first group of half-selected memory cells; and
means for sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell, to determine the data state of each selected memory cell;
wherein each of the first group of half-selected memory cells is coupled to a selected X-line or Y-line whose current flow is sensed; and
wherein the memory cells comprise an amorphous solid.
19. The integrated circuit of claim 18 wherein the memory cells comprise:
antifuse memory cells having a programming voltage in the range of about 5–20 volts.
20. The integrated circuit of claim 18 wherein the memory cells comprise:
fuse memory cells having a programming voltage in the range of about 5–20 volts.
21. The integrated circuit of claim 18 wherein:
the means for biasing the X-lines and Y-lines is configured so that no appreciable bias voltage is impressed across a second group of half-selected memory cells; and
each of the second group of half-selected memory cells is not coupled to a selected X-line or Y-line whose current flow is sensed.
22. The integrated circuit of claim 18 wherein:
the means for biasing the X-lines and Y-lines is configured so that no appreciable bias voltage is impressed across any half-selected memory cells.
23. The integrated circuit of claim 18 wherein:
the means for sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell is configured to sense while keeping any such current-sensed X-line or Y-line substantially unchanged in voltage.
24. The integrated circuit of claim 18 wherein:
the X-lines are always connected to a respective anode terminal of associated memory cells.
25. The integrated circuit of claim 18 wherein:
the X-lines are always connected to a respective cathode terminal of associated memory cells.
26. The integrated circuit of claim 24 wherein:
a selected X-line is either driven or sensed and the selected Y-line either sensed or driven, irrespective of which memory cell is selected.
27. The integrated circuit of claim 18 wherein the memory cells comprise a semiconductor material.
28. The integrated circuit of claim 18 wherein:
the memory cells comprise antifuse memory cells.
29. An integrated circuit comprising:
a memory array having at least two memory planes of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, each respective memory cell within a memory plane coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines associated with the memory plane;
means for biasing the X-lines and Y-lines so that a forward bias voltage of at least about 1 volt is impressed across one or more selected memory cells, and further so that no appreciable bias voltage is impressed across at least a first group of half-selected memory cells; and
means for sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell, to determine the data state of each selected memory cell;
wherein each of the first group of half-selected memory cells is coupled to a selected X-line or Y-line whose current flow is sensed; and
wherein the X-lines are connected to respective anode terminals of some associated memory cells, and to respective cathode terminals of other associated memory cells.
30. The integrated circuit of claim 29 wherein:
a selected X-line is either driven or sensed depending upon whether it connects to a respective anode terminal or a respective cathode terminal of a selected memory cell.
31. An integrated circuit comprising:
a memory array having at least two memory planes of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, each respective memory cell within a memory plane coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines associated with the memory plane;
means for biasing the X-lines and Y-lines so that a forward bias voltage of at least about 1 volt is impressed across one or more selected memory cells, and further so that no appreciable bias voltage is impressed across at least a first group of half-selected memory cells; and
means for sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell, to determine the data state of each selected memory cell;
wherein each of the first group of half-selected memory cells is coupled to a selected X-line or Y-line whose current flow is sensed; and
wherein the memory cells comprise an organic polymer.
32. An integrated circuit comprising:
a memory array having at least two memory planes of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, each respective memory cell within a memory plane coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines associated with the memory plane;
means for biasing the X-lines and Y-lines so that a forward bias voltage of at least about 1 volt is impressed across one or more selected memory cells, and further so that no appreciable bias voltage is impressed across at least a first group of half-selected memory cells; and
means for sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell, to determine the data state of each selected memory cell;
wherein each of the first group of half-selected memory cells is coupled to a selected X-line or Y-line whose current flow is sensed; and
wherein the memory cells comprise a phase change material.
33. In a memory array having at least two memory planes of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, each respective memory cell within a memory plane coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines associated with the memory plane, a method of sensing the data state of one or more selected memory cells comprising the steps of:
biasing the X-lines and Y-lines so that a forward bias voltage of at least about 1 volt is impressed across one or more selected memory cells, and further so that no appreciable bias voltage is impressed across at least a first group of half-selected memory cells; and
sensing current flow on the at least one of the respective X-line or respective Y-line associated with each selected memory cell relative to a noise current flowing in an associated noise detection line within the array, to determine the data state of each selected memory cell;
wherein each of the first group of half-selected memory cells is coupled to a selected X-line or Y-line whose current flow is sensed.
34. The method of claim 33 wherein:
each X-line or Y-line on a given layer of the array is associated with memory cells in a memory plane above the given layer, if such plane is present, and associated with memory cells in a memory plane below the given layer, if such plane is present.
35. The method of claim 34 wherein:
the memory cells comprise antifuse memory cells.
36. The method of claim 33 wherein the sensing step comprises:
sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell while keeping any such current-sensed X-line or Y-line substantially unchanged in voltage.
37. An integrated circuit comprising:
a memory array having at least two memory planes of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, each respective memory cell within a memory plane coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines associated with the memory plane;
means for biasing the X-lines and Y-lines so that a forward bias voltage of at least about 1 volt is impressed across one or more selected memory cells, and further so that no appreciable bias voltage is impressed across at least a first group of half-selected memory cells; and
means for sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell, to determine the data state of each selected memory cell;
wherein each of the first group of half-selected memory cells is coupled to a selected X-line or Y-line whose current flow is sensed; and
wherein the means for sensing current flow is configured to sense a current flowing outward from the memory array.
38. The integrated circuit of claim 37 wherein the means for sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell is configured to sense while keeping any such current-sensed X-line or Y-line substantially unchanged in voltage.
39. An integrated circuit comprising:
a memory array having at least two memory planes of memory cells with diode-like conduction characteristics for at least one of two memory cell data states, each respective memory cell within a memory plane coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines associated with the memory plane;
means for biasing the X-lines and Y-lines so that a forward bias voltage of at least about 1 volt is impressed across one or more selected memory cells, and further so that no appreciable bias voltage is impressed across at least a first group of half-selected memory cells; and
means for sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell relative to a noise current flowing in an associated noise detection line within the array, to determine the data state of each selected memory cell;
wherein each of the first group of half-selected memory cells is coupled to a selected X-line or Y-line whose current flow is sensed.
40. The integrated circuit of claim 39 wherein:
each X-line or Y-line on a given layer of the array is associated with memory cells in a memory plane above the given layer, if such plane is present, and associated with memory cells in a memory plane below the given layer, if such plane is present.
41. The integrated circuit of claim 40 wherein:
the memory cells comprise antifuse memory cells.
42. The integrated circuit of claim 39 wherein:
the means for sensing current flow on at least one of the respective X-line or respective Y-line associated with each selected memory cell is configured to sense while keeping any such current-sensed X-line or Y-line substantially unchanged in voltage.