Method and apparatus for accessing memories having a time-variant response over a PCI bus by using two-stage DMA transfers
View Patent ↗The invention relates to an apparatus and a method for accessing memories having a time-variant response over a PCI bus by using two-stage DMA transfers. The invention provides a method for executing a read request over a PCI bus by transferring the requested data from a main memory of a PCI card to a device located on the PCI bus, comprising the steps of obtaining an access request from a read access queue, transferring, by a first DMA transfer, the requested data from the main memory to a buffer memory on the PCI card, and transferring, by a second DMA transfer, the data from the buffer memory to the device.
1. A method for executing a mad request over a PCI bus by transferring data from a time-variant main memory of a first device to a second device, comprising the steps of:
obtaining an access request from a queue;
transferring, by a first DMA transfer, data from said time-variant main memory to a time-invariant second memory on said first device; and
transferring, by a second DMA transfer, said data from said time-invariant second memory to said second device.
2. The method of claim 1 , wherein said second DMA transfer is initiated and said access request is selected by a finite state machine which is associated with said queue.
3. The method of claim 1 , wherein said second DMA transfer is initiated after said data transfer to said time-invariant second memory is terminated.
4. The method of claim 1 , wherein said read request is a master read request hidden as a master write access of said first device.
5. The method of claim 4 , wherein said master read request is directed to a target command queue of a finite state machine.
6. The method of claim 1 , wherein said second device and said time-variant main memory are decoupled.
7. The method of claim 1 , wherein data polling is avoided by transforming master read cycles of said second device to master write cycles of said first device.
8. A method for executing a write request over a PCI bus by transferring requested data from it second device to a time-variant main memory of a fast device, comprising the steps of:
writing an access request to a queue;
transferring, by a first DMA transfer, data from said second device to a time-invariant second memory on said first device; and
transferring, by a second DMA transfer, said data from said time-invariant second memory to said time-variant main memory of said first device.
9. The method of claim 8 , wherein said time-variant access behavior of said time-variant main memory is taken into consideration for said second DMA transfer.
10. The method of claim 8 , wherein said first DMA transfer is initiated by said second device.
11. The method of claim 8 , wherein said second DMA transfer is initiated and said access request is selected by a finite state machine, which is associated with said queue.
12. The method of claim 8 , wherein said second DMA transfer is initiated after said data transfer to said time-invariant second memory is terminated.
13. The method of claim 8 , wherein said second device and said time-variant main memory are decoupled.
14. An apparatus for executing a read request over a PCI bus, comprising:
a queue for storing a read access request;
a time-variant main memory for storing data to be transferred;
a time-invariant buffer memory for buffer storage of said data, whereby data transfer to said time-variant buffer memory is accomplished by a first DMA transfer,
a device located on the PCI bus for receiving said data, whereby data transfer from said time-variant buffer memory to said device is accomplished by a second DMA transfer; and
a finite state machine associated with said queue for selecting an access request.
15. The apparatus of claim 14 , wherein said time-variant main memory and said time-invariant buffer memory are located on a PCI card.
16. The apparatus of claim 15 , wherein data polling is avoided by transforming master read cycles of said device to master write cycles of said PCI card.
17. The apparatus of claim 14 , wherein said finite state machine is adapted to initiate said second DMA transfer.
18. The apparatus of claim 14 , wherein said second DMA transfer is initiated after said data transfer to said time-invariant buffer memory is terminated.
19. The apparatus of claim 14 , wherein said device and said time-variant main memory are decoupled.
20. An apparatus for executing a write request over a PCI bus, comprising:
a queue for storing a write access request;
a device located on a PCI bus for storing data to be transferred;
a time-variant main memory for receiving said data;
a time-invariant buffer memory for buffer storage of said data, whereby data warder to said time-invariant buffer memory is accomplished by a first DMA transfer and data transfer from said time-invariant buffer memory to said time-variant main memory is accomplished by a second DMA transfer; and
a finite state machine associated with said queue for selecting an access request.
21. The apparatus of claim 20 , wherein said invariant access behavior of said main memory is taken into consideration for said second DMA transfer.
22. The apparatus of claim 20 , wherein said time-variant main memory and said time-invariant buffer memory are located on a PCI card.
23. The apparatus of claim 20 , wherein said first DMA transfer is initiated by said device.
24. The apparatus of claim 20 , wherein said finite state machine is adapted to initiate said second DMA transfer.
25. The apparatus of claim 20 , wherein said second DMA transfer is initiated after said data transfer to said time-invariant buffer memory is terminated.
26. The apparatus of claim 20 , wherein said device and said time-variant main memory are decoupled.