IP Library › Granted Patent US 6,677,192
Granted Patent Utility
US 6,677,192 · Confirmation No. 4895

Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits

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2010-04-02 N570 Communication - Re: Power of Attorney (PTOL-308) 1 View
2010-04-02 N570 Communication - Re: Power of Attorney (PTOL-308) 1 View
2010-03-25 PA.. Power of Attorney 1 View
2010-03-25 R3.73 Assignee showing of ownership per 37 CFR 3.73 1 View
2010-03-25 N417 Electronic Filing System Acknowledgment Receipt 2 View
2005-03-10 EBCC.AD Notice of Change of Address Place in File Wrapper Due to Electronic Business Center(EBC) Customer Number Update 1 View
2003-09-24 IFEE Issue Fee Payment (PTO-85B) 2 View
2003-09-24 LET. Miscellaneous Incoming Letter 4 View
2003-09-24 DRW Drawings-only black and white line drawings 17 View
2001-07-16 TRNA Transmittal of New Application 4 View
2001-07-16 SPEC Specification 23 View
2001-07-16 CLM Claims 3 View
2001-07-16 ABST Abstract 1 View
2001-07-16 DRW Drawings-only black and white line drawings 17 View
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Quick Facts
Patent No.
US 6,677,192
App. No.
09/906,545
Filed
2001-07-16
Granted
2004-01-13
Art Unit
2813
PTA
-271 days