Patent Assignment
Reel/Frame 023848/0183
Assignment of Assignor's Interest
Recorded: 2010-01-26
Pages: 20
Assignor
AMBERWAVE SYSTEMS CORPORATION
Executed: 2009-11-22
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
NO. 8, LI-HSIN RD. 6, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, 300-77, TAIWAN
Covered Properties
(83)
Back-Biasing to Populate Strained Layer Quantum Wells
Methods of Forming Reacted Conductive Gate Electrodes
Reacted Conductive Gate Electrodes
Semiconductor Devices Having Strained Dual Channel Layers
Methods of Fabricating Semiconductor Devices Having Strained Dual Channel Layers
Methods of Fabricating Semiconductor Structures Having Epitaxially Grown Source and Drain Elements
Methods of Fabricating Semiconductor Structures Having Epitaxially Grown Source and Drain Elements
Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
Elevated Source and Drain Elements for Strained-Channel Heterojuntion Field-Effect Transistors
Dual-Channel Cmos Transistors with Differentially Strained Channels
Strained-Semiconductor-On-Insulator Finfet Device Structures
Methods of Forming Strained-Semiconductor-on-Insulator Finfet Device Structures
Strained-Semiconductor-On-Insulator Device Structures with Elevated Source/Drain Regions
Strained Germanium-on-Insulator Device Structures
Strained-Semiconductor-On-Insulator Device Structures
Strained-Semiconductor-On-Insulator Device Structures
Methods for Forming Strained-Semiconductor-on-Insulator Device Structures by Use of Cleave Planes
Methods for Forming Strained-Semiconductor-on-Insulator Device Structures by Mechanically Inducing Strain
Control of Strain in Device Layers by Prevention of Relaxation
Control of Strain in Device Layers by Selective Relaxation
Methods of Forming Dynamic Random Access Memory Trench Capacitors
Dynamic Random Access Memory Trench Capacitors
Dynamic Random Access Memory Trench Capacitors
Buried-Channel Devices and Substrates for Fabrication of Semiconductor-Based Devices
Dual Layer Cmos Devices
Methods of Fabricating Dual Layer Semiconductor Devices
Semiconductor Structures Employing Strained Material Layers with Defined Impurity Gradients and Methods for Fabricating Same
Rf Circuits Including Transistors Having Strained Material Layers
Methods for Fabricating Strained Layers on Semiconductor Substrates
Methods for Fabricating Strained Layers on Semiconductor Substrates
Method of Producing High Quality Relaxed Silicon Germanium Layers
Low Threading Dislocation Density Relaxed Mismatched Epilayers Without High Temperature Growth
Low Threading Dislocation Density Relaxed Mismatched Epilayers Without High Temperature Growth
Low Threading Dislocation Density Relaxed Mismatched Epilayers Without High Temperature Growth
Heterointegration of Materials Using Deposition and Bonding
Heterointegration of Materials Using Deposition and Bonding
Patent:
6,602,613 →
Application:
09/764,182 →
Heterointegration of Materials Using Deposition and Bonding
Patent:
6,750,130 →
Application:
09/764,177 →
Buried Channel Strained Silicon Fet Using a Supply Layer Created Through Ion Implantation
Buried Channel Strained Silicon Fet Using a Supply Layer Created Through Ion Implantation
Buried Channel Strained Silicon Fet Using a Supply Layer Created Through Ion Implantation
Silicon Wafer with Embedded Optoelectronic Material for Monolithic Oeic
Silicon Wafer with Embedded Optoelectronic Material for Monolithic Oeic
Silicon Wafer with Embedded Optoelectronic Material for Monolithic Oeic
Gate Technology for Strained Surface Channel and Strained Buried Channel Mosfet Devices
Gate Technology for Strained Surface Channel and Strained Buried Channel Mosfet Devices
Gate Technology for Strained Surface Channel and Strained Buried Channel Mosfet Devices
Method of Fabricating Cmos Inverter and Integrated Circuits Utilizing Strained Silicon Surface Channel Mosfets
Method of Fabricating Cmos Inverter and Integrated Circuits Utilizing Strained Surface Channel Mosfets
Relaxed INXGA1-Xas Layers Integrated with Si
Patent:
6,594,293 →
Application:
09/779,917 →
Relaxed INXGA1-Xas Layers Integrated with Si
Relaxed Silicon Germanium Platform for High Speed Cmos Electronics and High Speed Analog Circuits
Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits
Patent:
6,677,192 →
Application:
09/906,545 →
Relaxed Silicon Germanium Platform for High Speed Cmos Electronics and High Speed Analog Circuits
Patent:
6,703,688 →
Application:
09/906,200 →
Relaxed Sige Platform for High Speed Cmos Electronics and High Speed Analog Circuits
Relaxed Sige Platform for High Speed Cmos Electronics and High Speed Analog Circuits
Relaxed Silicon Germanium Platform for High Speed Cmos Electronics and High Speed Analog Circuits
Relaxed Silicon Germanium Platform for High Speed Cmos Electronics and High Speed Analog Circuits
Relaxed Silicon Germanium Platform for High Speed Cmos Electronics and High Speed Analog Circuits
Relaxed Silicon Germanium Platform for High Speed Cmos Electronics and High Speed Analog Circuits
Patent:
6,593,641 →
Application:
09/906,550 →
Relaxed Silicon Germanium Platform for High Speed Cmos Electronics and High Speed Analog Circuits
Method of Forming Multiple Gate Insulators on a Strained Semiconductor Heterostructure
Method of Forming Multiple Gate Insulators on a Strained Semiconductor Heterostructure
Method of Selective Removal of Sige Alloys
Semiconductor Heterostructures and Related Methods
Methods of Fabricating Semiconductor Heterostructures
Semiconductor Heterostructures Having Reduced Dislocation Pile-Ups
Gate Material for Semiconductor Device Fabrication
Gate Material for Semiconductor Device Fabrication
Gate Material for Semiconductor Device Fabrication
Methods for Selective Placement of Dislocation Arrays
Methods for Preserving Strained Semiconductor Substrate Layers During Cmos Processing
Methods for Preserving Strained Semiconductor Substrate Layers During Cmos Processing
Methods for Preserving Strained Semiconductor Substrate Layers During Cmos Processing
Methods for Preserving Strained Semiconductor Substrate Layers During Cmos Processing
Methods for Preserving Strained Semiconductor Substrate Layers During Cmos Processing
Reduction of Dislocation Pile-Up Formation During Relaxed Lattice-Mismatched Epitaxy
Semiconductor Structures with Structural Homogeneity
Shallow Trench Isolation Process
Shallow Trench Isolation Process
Methods of Forming Hybrid Fin Field-Effect Transistor Structures
Methods for Forming Dielectrics and Metal Electrodes
Solutions for Integrated Circuit Integration of Alternative Active Area Materials
Lattice-Mismatched Semiconductor Structures on Insulators
Related Assignments
(15)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 23, 2002
From: CURRIE, MATTHEW T.; LOCHTEFELD, ANTHONY J.; FITZGERALD, EUGENE A.
To: AMBERWAVE SYSTEMS CORPORATION
Reel/Frame 013312/0004 →
Assignment of Assignor's Interest
Oct 17, 2002
From: LOCHTEFELD, ANTHONY; LANGDO, THOMAS A.; WESTHOFF, RICHARD
To: AMBERWAVE SYSTEMS CORPORATION
Reel/Frame 013399/0463 →
Assignment of Assignor's Interest
Nov 4, 2002
From: CURRIE, MATTHEW T.; HAMMOND, RICHARD
To: AMBERWAVE SYSTEMS CORPORATION
Reel/Frame 013452/0338 →
Assignment of Assignor's Interest
Nov 4, 2002
From: HAMMOND, RICHARD; BRAITHWAITE, GLYN
To: AMBERWAVE SYSTEMS CORPORATION
Reel/Frame 013452/0225 →
Assignment of Assignor's Interest
Dec 12, 2003
From: CURRIE, MATTHEW T.; LOCHTEFELD, ANTHONY J.; LEITZ, CHRISTOPHER W.; FITZGERALD, EUGENE A.
To: AMBERWAVE SYSTEMS CORPORATION
Reel/Frame 014781/0487 →
Assignment of Assignor's Interest
Apr 12, 2004
From: LOCHTEFELD, ANTHONY J.; LANGDO, THOMAS A.
To: AMBERWAVE SYSTEMS CORPORATION
Reel/Frame 015199/0322 →
Assignment of Assignor's Interest
Jun 9, 2005
From: LOCHTEFELD, ANTHONY J.; LANGDO, THOMAS A.; HAMMOND, RICHARD; CURRIE, MATTHEW T.
To: AMBERWAVE SYSTEMS CORPORATION
Reel/Frame 016667/0014 →
Assignment of Assignor's Interest
Jun 10, 2005
From: CURRIE, MATTHEW T.; HAMMOND, RICHARD
To: AMBERWAVE SYSTEMS CORPORATION
Reel/Frame 016676/0329 →
Assignment of Assignor's Interest
Jun 10, 2005
From: LOCHTEFELD, ANTHONY J.; LANGDO, THOMAS A.
To: AMBERWAVE SYSTEMS CORPORATION
Reel/Frame 016676/0206 →
Assignment of Assignor's Interest
Jul 25, 2005
From: LANGDO, THOMAS A.; CURRIE, MATTHEW T.; BRAITHWAITE, GLYN; HAMMOND, RICHARD
To: AMBERWAVE SYSTEMS CORPORATION
Reel/Frame 016802/0359 →
Assignment of Assignor's Interest
Jul 25, 2005
From: LANGDO, THOMAS A.; CURRIE, MATTHEW T.; HAMMOND, RICHARD; LOCHTEFELD, ANTHONY J.
To: AMBERWAVE SYSTEMS CORPORATION
Reel/Frame 016799/0239 →
Assignment of Assignor's Interest
Sep 15, 2005
From: LANGDO, THOMAS A.; CURRIE, MATTHEW T.; BRAITHWAITE, GLYN; HAMMOND, RICHARD
To: AMBERWAVE SYSTEMS CORPORATION
Reel/Frame 016991/0743 →
Assignment of Assignor's Interest
Sep 11, 2006
From: LOCHTEFELD, ANTHONY J.; LANGDO, THOMAS A.
To: AMBERWAVE SYSTEMS CORPORATION
Reel/Frame 018225/0563 →
Assignment of Assignor's Interest
Dec 8, 2006
From: CURRIE, MATTHEW T.; LOCHTEFELD, ANTHONY J.; FITZGERALD, EUGENE A.; LEITZ, CHRISTOPHER W.
To: AMBERWAVE SYSTEMS CORPORATION
Reel/Frame 018600/0173 →
Assignment of Assignor's Interest
Jan 16, 2007
From: CURRIE, MATTHEW T.; LOCHTEFELD, ANTHONY J.; LEITZ, CHRISTOPHER W.; FITZGERALD, EUGENE A.
To: AMBERWAVE SYSTEMS CORPORATION
Reel/Frame 018760/0405 →