Control of strain in device layers by selective relaxation
The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. Strain in the strained semiconductors is controlled for improved device performance.
1. A structure comprising:
a substantially strained layer disposed over and contacting a dielectric layer disposed over a semiconductor substrate, the substantially strained layer having a first portion and a second portion;
a first transistor having
a first strained channel, the first channel disposed in the first portion of the substantially strained layer, and
a first strain-inducing stressor inducing only a portion of the strain in the first channel; and
a second transistor having
a second strained channel, the second channel disposed in the second portion of the substantially strained layer, and
at least one second strain-inducing stressor inducing substantially all of the strain in the second channel.
2. The structure of claim 1 , wherein the first transistor comprises an NMOSFET, and the second transistor comprises a PMOSFET.
3. The structure of claim 1 , wherein at least one of the first and second transistors comprises a finFET.
4. The structure of claim 1 , wherein the type of strain induced by the first strain-inducing stressor is different from the type of strain induced by the at least one second strain-inducing stressor.
5. The structure of claim 4 , wherein the type of strain induced by the first strain-inducing stressor is tensile and the type of strain induced by the at least one second strain-inducing stressor is compressive.
6. The structure of claim 4 , wherein the type of strain induced by the first strain-inducing stressor is compressive and the type of strain induced by the at least one second strain-inducing stressor is tensile.
7. The structure of claim 1 , wherein the first strain-inducing stressor is at least one of (i) strain-inducing source and drain regions defined in respective recesses; (ii) an overlayer disposed over a gate of the first transistor; (iii) a shallow-trench isolation region; (iv) a gate electrode; (v) metal-semiconductor alloy disposed on at least one of a gate, a source region, or a drain region; (vi) a sidewall spacer of the first transistor; (vii) at least one void disposed below at least one of source region, a drain region, or a channel of the first transistor; or (viii) a package.
8. The structure of claim 1 , wherein the at least one second strain-inducing stressor is at least one of (i) strain-inducing source and drain regions defined in respective recesses; (ii) an overlayer disposed over a gate of the second transistor; (iii) a shallow-trench isolation region; (iv) a gate electrode; (v) metal-semiconductor alloy disposed on at least one of a gate, a source region, or a drain region of the second transistor; (vi) a sidewall spacer; (vii) at least one void disposed below at least one of source region, a drain region, or a channel of the second transistor; or (viii) a package.
9. The structure of claim 1 , wherein the type of strain induced by the second strain-inducing stressor is different from a type of strain in the substantially strained layer.
10. A structure comprising:
a semiconductor layer disposed over and contacting a dielectric layer disposed over a semiconductor substrate, the semiconductor layer having a first portion and a second portion;
a first transistor having
a first strained channel, the first channel disposed in the first portion of the semiconductor layer, and
a plurality of first strain-inducing stressors including strain in the first channel; and
a second transistor having
a second strained channel, the second channel disposed in the second portion of the semiconductor layer, and
a plurality of second strain-inducing stressors inducing strain in the second channel.
11. The structure of claim 10 , wherein the plurality of first strain-inducing stressors comprises at least one of (i) strain-inducing source and drain regions defined in respective recesses; (ii) an overlayer disposed over a gate of the first transistor; (iii) a shallow-trench isolation region; (iv) a gate electrode; (v) metal-semiconductor alloy disposed on at least one of a gate, a source region, and a drain region; (vi) a sidewall spacer of the first transistor; (vii) at least one void disposed below at least one of source region; a drain region, and a channel of the first transistor; or (viii) a package.
12. The structure of claim 10 , wherein the plurality of second strain-inducing stressors comprises at least one of (i) strain-inducing source and drain regions defined in respective recesses; (ii) an overlayer disposed over a gate of the second transistor; (iii) a shallow-trench isolation region; (iv) a gate electrode; (v) metal-semiconductor alloy disposed on at least one of a gate, a source region, and a drain region of the second transistor; (vi) a sidewall spacer; (vii) at least one void disposed below at least one of source region, a drain region, and a channel of the second transistor; or (viii) a package.
13. The structure of claim 10 , wherein the plurality of first strain-inducing stressors comprises (i) a first overlayer disposed over a gate of the first transistor and (ii) a gate electrode of the first transistor, and the plurality of second strain-inducing stressors comprises (i) a second overlayer disposed over a gate of the second transistor and (ii) strain-inducing source and drain regions of the second transistor defined in respective recesses.
14. The structure of claim 13 , wherein the first transistor comprises an NMOSFET, and the second transistor comprises a PMOSFET.
15. The structure of claim 10 , wherein the type of strain induced by the plurality of first strain-inducing stressors is different from the type of strain induced by the plurality of second strain-inducing stressors.
16. The structure of claim 15 , wherein the type of strain induced by the plurality of first strain-inducing stressors is tensile and the type of strain induced by the plurality of second strain-inducing stressors is compressive.
17. The structure of claim 15 , wherein the type of strain induced by the plurality of first strain-inducing stressors is compressive and the type of strain induced by the plurality of second strain-inducing stressors is tensile.