Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
1. A method of fabricating a semiconductor structure, the method comprising the steps of:
providing a first strained layer on a substrate;
providing a spacer layer thereover;
providing a surface strained layer over the spacer layer;
forming at least one surface-channel device on the structure, the at least one surface-channel device having a carrier channel in the surface strained layer but not in the first strained layer; and
forming at least one buried-channel device on the structure, the at least one buried-channel device having a carrier channel in the first strained layer but not in the surface strained layer.
2. The method of claim 1 , wherein the at least one surface-channel device is a MOSFET comprising a gate dielectric over the strained surface layer.
3. The method of claim 1 , wherein wherein the at least one buried-channel device is a FET comprising a thinned portion of the surface strained layer and a gate dielectric thereover.
4. The method of claim 1 , further comprising the step of providing a dopant supply layer above and adjacent the first strained layer.
5. The method of claim 1 , further comprising the step of providing a dopant supply layer below and adjacent the first strained layer.
6. The method of claim 1 , wherein the spacer layer is a relaxed composition of silicon and germanium.
7. The method of claim 1 , wherein at least one of the strained layers is silicon.
8. The method of claim 1 , wherein both of the strained layers are silicon.
9. The method of claim 1 , wherein at least the surface strained layer comprises Ge.
10. The method of claim 1 , wherein at least the first strained layer comprises Ge.
11. The method of claim 1 , wherein the first strained layer is compressively strained.
12. The method of claim 1 , wherein the first strained layer is tensilely strained.
13. The method of claim 1 , wherein the at least one buried-channel device is a FET comprising a gate dielectric disposed directly on the spacer layer.
14. A method of fabricating a semiconductor structure, the method comprising the steps of:
providing a first strained layer on a substrate;
providing a spacer layer thereover; and
providing surface strained layer over the spacer layer,
wherein the substrate comprises at least one planarized surface having an average roughness level no greater than 2 nm.
15. A method of fabricating a semiconductor structure, the method comprising the steps of:
providing a first strained layer on a substrate;
providing a spacer layer thereover; and
providing surface strained layer over the spacer layer,
wherein the substrate is fabricated according to steps comprising:
providing a relaxed SiGe layer;
planarizing the relaxed SiGe layer; and
providing at least one regrown layer on the relaxed SiGe layer following planarization.
16. A method of fabricating a semiconductor structure, the method comprising the steps of:
providing a first strained semiconductor layer on a substrate;
providing a spacer layer thereover;
providing surface strained layer over the spacer layer; and
providing an insulator between the substrate and the first strained semiconductor layer.
17. The method of claim 16 , wherein the insulator is SiO 2 .
18. A method of fabricating a semiconductor structure, the method comprising the steps of:
providing a first strained semiconductor layer on a substrate;
providing a spacer layer thereover;
providing surface strained layer over the spacer layer; and
removing the surface strained layer and the spacer layer to form a carrier channel of a surface-channel device in the first strained semiconductor layer.
19. The method of claim 18 , wherein the surface-channel device is a MOSFET comprising a gate dielectric over the first strained layer.