Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy

1. A method for forming a semiconductor structure, comprising the steps of:

providing a semiconductor substrate having a top surface and a rough edge angled away from the surface;

thereafter growing a cap layer over the top surface of the substrate, the cap layer being substantially relaxed, having a uniform composition, and having a lattice constant different from a lattice constant of the semiconductor substrate; and

polishing the rough edge of the substrate after at least a portion of the cap layer is grown.

2. The method of claim 1 , wherein the cap layer has a density of dislocation pile-ups of less than 20/cm.

3. The method of claim 1 , wherein the cap layer has a threading dislocation density of less than 10 7 /cm 2 .

4. The method of claim 1 , wherein the cap layer comprises at least one of a group II, a group III, a group IV, a group V, and a group VI element.

5. The method of claim 4 , wherein the cap layer comprises silicon and germanium.

6. The method of claim 5 , wherein the cap layer comprises approximately 20% germanium.

7. The method of claim 1 , wherein at least a portion of the cap layer is formed by growth at a growth temperature greater than 600° C.

8. The method of claim 7 , wherein at least a portion of the cap layer is formed at a growth temperature greater than 900° C.

9. The method of claim 1 , further comprising:

annealing at least a portion of the cap layer at a temperature greater than 600° C.

10. The method of claim 9 , wherein the portion of the cap layer is annealed at a temperature greater than 900° C.

11. The method of claim 1 , wherein providing the semiconductor substrate with the rough edge comprises roughening the edge of the semiconductor substrate.

12. The method of claim 1 , further comprising:

forming a strained layer over the relaxed cap layer.

13. The method of claim 12 , further comprising:

planarizing at least a portion of the relaxed cap layer prior to the formation of the strained layer.

14. The method of claim 12 , further comprising:

forming a relaxed compositionally graded layer over the substrate, proximate the relaxed cap layer.

15. The method of claim 1 , further comprising:

forming a p-type metal-oxide-semiconductor (PMOS) transistor by:

(i) forming a gate dielectric portion over a portion of the relaxed cap layer,

(ii) forming a gate over the gate dielectric portion, the gate comprising a conducting layer,

(iii) forming a source and a drain proximate the gate dielectric portion, the source and drain including p-type dopants.

16. The method of claim 1 , further comprising:

forming an n-type metal-oxide-semiconductor (NMOS) transistor by:

(i) forming a gate dielectric portion over a portion of the relaxed cap layer,

(ii) forming a gate over the gate dielectric portion, the gate comprising a conducting layer,

(iii) forming a source and a drain proximate the gate dielectric portion, the source and drain including n-type dopants.

17. The method of claim 1 -further comprising:

forming a p-type metal-oxide-semiconductor (PMOS) transistor by:

(i) forming a first gate dielectric portion over a first portion of the relaxed cap layer,

(ii) forming a first gate over the first gate dielectric portion, the first gate comprising a first conducting layer,

(iii) forming a first source and a first drain proximate the first gate dielectric portion, the first source and first drain including p-type dopants; and forming an n-type metal-oxide-semiconductor (NMOS) transistor by:

(i) forming a second gate dielectric portion over a second portion of the relaxed cap layer,

(ii) forming a second gate over the second gate dielectric portion, the second gate comprising a second conducting layer,

(iii) forming a second source and a second drain proximate the second gate dielectric portion, the second source and second drain including n-type dopants.

18. The method of claim 1 , wherein the rough edge of the substrate defines an edge plane, the top surface defines a surface plane, and the edge plane and the surface plane are non-coplanar.

19. The method of claim 1 , wherein the substrate has a bottom surface and the rough edge is disposed between the top and bottom surfaces.

20. A method for forming a semiconductor structure, comprising the steps of:

providing a semiconductor substrate having a top surface and a rough edge angled away from the surface;

thereafter forming a relaxed compositionally graded layer over the top surface of the substrate;

polishing the rough edge of the substrate after at least a portion of the graded layer is formed; and

forming a cap layer over the graded layer, the cap layer being substantially relaxed, having a uniform composition, and having a lattice constant different from a lattice constant of the semiconductor substrate,

wherein the graded layer is proximate the relaxed cap layer.

21. The method of claim 20 , wherein the graded layer has a density of dislocation pile-ups of less than 20/cm.

22. The method of claim 20 , wherein the graded layer has a threading dislocation density of less than 10 7 /cm 2 .

23. The method of claim 20 , wherein the graded layer comprises at least one of a group II, a group III, a group IV, a group V, and a group VI element.

24. The method of claim 23 , wherein the graded layer comprises silicon and germanium.

25. The method of claim 24 , wherein the graded layer has a grade rate greater than 5% germanium per micrometer.

26. The method of claim 20 , wherein the graded layer is graded to a concentration of 20% germanium.

27. The method of claim 20 , wherein at least a portion of the graded layer is formed by growth at a growth temperature greater than 600° C.

28. The method of claim 27 , wherein at least a portion of the graded layer is formed at a growth temperature greater than 900° C.

29. The method of claim 20 , further comprising: annealing at least a portion of the graded layer at a temperature greater than 600° C.

30. The method of claim 29 , wherein the portion of the graded layer is annealed at a temperature greater than 900° C.

31. The method of claim 20 , wherein the rough edge of the substrate defines an edge plane, the top surface defines a surface plane, and the edge plane and the surface plane are non-coplanar.

32. The method of claim 20 , wherein the substrate has a bottom surface and the rough edge is disposed between the top and bottom surfaces.

33. A method for forming a semiconductor structure, the method comprising the steps of:

providing a semiconductor substrate having a top surface and a rough edge angled away from the surface;

thereafter forming a relaxed compositionally graded layer over the top surface of the substrate;

forming a cap layer proximate the graded layer, the cap layer being substantially relaxed, having a uniform composition, and having a lattice constant different from a lattice constant of the semiconductor substrate;

forming a strained layer over the relaxed cap layer; and

polishing the rough edge of the substrate after at least a portion of the graded layer is formed.

34. The method of claim 33 , wherein the rough edge is polished after at least a portion of the relaxed cap layer is formed.

35. The method of claim 33 , wherein the rough edge of the substrate defines an edge plane, the top surface defines a surface plane, and the edge plane and the surface plane are non-coplanar.

36. The method of claim 33 , wherein the substrate has a bottom surface and the rough edge is disposed between the top and bottom surfaces.

37. A method for forming a semiconductor structure, comprising the steps of:

providing a semiconductor substrate having a top surface and a rough outer face not coplanar with the top surface;

thereafter growing a cap layer over the top surface of the substrate, the cap layer being substantially relaxed, having a uniform composition, and having a lattice constant different from a lattice constant of the semiconductor substrate; and

polishing the rough outer face of the substrate after at least a portion of the cap layer is grown.

38. The method of claim 37 , wherein the rough outer face is substantially perpendicular to the top surface.

39. A method for forming a semiconductor structure, comprising the steps of:

providing a semiconductor substrate having a top surface and a rough outer face not coplanar with the top surface;

thereafter forming a relaxed compositionally graded layer over the top surface of the substrate;

polishing the rough outer face of the substrate after at least a portion of the graded layer is formed; and

forming a cap layer over the graded layer, the cap layer being substantially relaxed, having a uniform composition, and having a lattice constant different from a lattice constant of the semiconductor substrate,

wherein the graded layer is proximate the relaxed cap layer.

40. The method of claim 39 , wherein the rough outer face is substantially perpendicular to the top surface.

41. A method for forming a semiconductor structure, the method comprising the steps of:

providing a semiconductor substrate having a top surface and a rough outer face not coplanar with the top surface;

thereafter forming a relaxed compositionally graded layer over the top surface of the substrate;

forming a cap layer proximate the graded layer, the cap layer being substantially relaxed, having a uniform composition, and having a lattice constant different from a lattice constant of the semiconductor substrate;

forming a strained layer over the relaxed cap layer; and

polishing the rough outer face of the substrate after at least a portion of the graded layer is formed.

42. The method of claim 41 , wherein the rough outer face is substantially perpendicular to the top surface.

43. A method for forming a semiconductor structure, comprising the steps of:

providing a semiconductor substrate having a top surface, a bottom surface, and a rough outer face disposed between the top and bottom surfaces;

thereafter growing a cap layer over the top surface of the substrate, the cap layer being substantially relaxed, having a uniform composition, and having a lattice constant different from a lattice constant of the semiconductor substrate; and

polishing the rough outer face of the substrate after at least a portion of the cap layer is grown.

44. A method for forming a semiconductor structure, comprising the steps of:

providing a semiconductor substrate having a top surface, a bottom surface, and a rough outer face disposed between the top and bottom surfaces;

forming a relaxed compositionally graded layer over the top surface of the substrate having the rough edge; and

forming a cap layer over the graded layer, the cap layer being substantially relaxed and having a uniform composition, and having a lattice constant different from a lattice constant of the semiconductor substrate,

wherein the rough outer face has a roughness greater than 10 angstroms.

45. A method for forming a semiconductor structure, comprising the steps of:

providing a semiconductor substrate having a top surface, a bottom surface, and a rough outer face disposed between the top and bottom surfaces;

thereafter forming a relaxed compositionally graded layer over the top surface of the substrate;

polishing the rough outer face of the substrate after at least a portion of the graded layer is formed; and

forming a cap layer over the graded layer, the cap layer being substantially relaxed, having a uniform composition, and having a lattice constant different from a lattice constant of the semiconductor substrate,

wherein the graded layer is proximate the relaxed cap layer.

46. A method for forming a semiconductor structure, the method comprising the steps of:

providing a semiconductor substrate having a top surface defining a surface plane, a bottom surface, and a rough outer face disposed between the top and bottom surfaces;

thereafter forming a relaxed compositionally graded layer over the top surface of the substrate;

forming a cap layer proximate the graded layer, the cap layer being substantially relaxed, having a uniform composition, and having a lattice constant different from a lattice constant of the semiconductor substrate;

forming a strained layer over the relaxed cap layer; and

polishing the rough outer face of the substrate after at least a portion of the graded layer is formed.