Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits
Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
1. A method comprising:
providing a substrate; and
providing a first strained layer disposed above the substrate, the first strained layer having an average surface roughness of no more than approximately 2 nm,
wherein the first strained layer is compressively strained.
2. The method of claim 1 , wherein the substrate comprises Si.
3. The method of claim 1 , wherein the first strained layer comprises Ge.
4. The method of claim 1 , wherein the first strained layer has a surface roughness of less than approximately 0.77 nm.
5. The method of claim 1 , further comprising providing an insulator layer disposed beneath the first strained layer.
6. The method of claim 5 , wherein the step of providing an insulator layer comprises wafer bonding.
7. The method of claim 1 , further comprising providing a relaxed layer disposed beneath the strained layer.
8. The method of claim 7 , wherein the relaxed layer has an average surface roughness of less than approximately 2 nm.
9. The method of claim 8 , further comprising planarizing the relaxed layer to reduce surface roughness.
10. The method of claim 7 , wherein the step of providing a relaxed layer comprises epitaxial growth.
11. The method of claim 7 , wherein the step of providing a relaxed layer comprises wafer bonding.
12. The method of claim 7 , wherein the relaxed layer comprises SiGe.
13. The method of claim 12 , wherein the substrate comprises a graded-composition SiGe layer.
14. The method of claim 12 , wherein the relaxed layer has an average surface roughness of less than approximately 0.77 nm.
15. The method of claim 12 , further comprising providing a regrown SiGe layer on the relaxed layer.
16. The method of claim 15 , wherein the regrown layer has a thickness of less than approximately 2 μm.
17. The method of claim 15 , wherein the regrown layer has a thickness of less than approximately 0.5 μm.
18. The method of claim 15 , wherein the regrown layer is substantially lattice-matched to the relaxed layer.
19. The method of claim 1 , further comprising providing a second strained layer disposed above the first strained layer.
20. The method of claim 1 , further comprising providing a spacer layer disposed above the first strained layer.
21. The method of claim 20 , wherein the spacer layer has a thickness of less than approximately 5 nm.
22. The method of claim 20 , wherein the first strained layer comprises Ge and the spacer layer consists essentially of Si.
23. The method of claim 20 , further comprising providing a second strained layer disposed above the spacer layer.
24. The method of claim 23 , further comprising providing a gate stack disposed above the second strained layer.
25. The method of claim 20 , wherein the spacer layer comprises Ge.
26. The method of claim 20 , further comprising providing a gate stack disposed above the spacer layer.
27. The method of claim 26 , further comprising providing supply layer dopants located in the spacer layer.
28. The method of claim 27 , wherein the supply layer dopants are provided by implantation.
29. The method of claim 26 , further comprising providing supply layer dopants located below the strained layer.
30. The method of claim 29 , wherein the supply layer dopants are provided by implantation.
31. The method of claim 1 , wherein the first strained layer has an average surface roughness of less than approximately 0.77 nm.
32. The method of claim 31 , further comprising providing a gate stack disposed above the first strained layer.
33. The method of claim 31 , further comprising providing a relaxed layer disposed beneath the strained layer.
34. The method of claim 33 , wherein the relaxed layer comprises SiGe.
35. The method of claim 1 , further comprising providing a gate stack disposed above the first strained layer.
36. The method of claim 35 , further comprising providing metal silicide regions.
37. The method of claim 1 , wherein the step of providing the strained layer comprises epitaxial growth.
38. The method of claim 1 , wherein the step of providing the strained layer comprises wafer bonding.
39. A method comprising:
providing a substrate;
providing an insulator layer over the substrate;
providing a first strained layer disposed above the substrate and the insulator layer, the first strained layer having an average surface roughness of no more than approximately 2 nm,
wherein the insulator layer comprises SiO 2 and the first strained layer consists essentially of Si.
40. The method of claim 39 , wherein the step of providing an insulator layer comprises wafer bonding.
41. The method of claim 39 , wherein the first strained layer is disposed in contact with a layer of SiGe disposed over and in contact with the insulator layer.
42. A method comprising:
providing a substrate;
providing a first strained layer disposed above the substrate, the first strained layer having an average surface roughness of no more than approximately 2 nm;
providing a gate stack disposed above the first strained layer; and
providing metal silicide regions,
wherein the metal silicide regions comprise alloyed metal-SiGe.
43. A method comprising:
providing a substrate;
providing a first strained layer disposed above the substrate, the first strained layer having an average surface roughness of no more than approximately 2 nm;
providing a gate stack disposed above the first strained layer; and
providing metal silicide regions,
wherein the metal is selected from the group consisting of: Ti, Co, and Ni.
44. A method comprising:
providing a substrate;
providing a first strained layer disposed above the substrate, the first strained layer having an average surface roughness of no more than approximately 2 nm;
providing a gate stack disposed above the first strained layer; and
providing metal silicide regions,
wherein the step of providing metal silicide regions comprises deposition followed by annealing.
45. A method comprising:
providing a substrate;
providing a first strained layer disposed above the substrate, the first strained layer having an average surface roughness of no more than approximately 2 nm;
providing a gate stack disposed above the first strained layer;
providing metal silicide regions; and
providing source and drain contact areas.
46. The method of claim 45 , further comprising providing an additional SiGe or Ge layer in the source and drain contact areas prior to providing metal silicide regions.
47. The method of claim 46 , further comprising providing an additional Si layer above the SiGe or Ge layer prior to providing metal silicide regions.
48. A method comprising:
providing a substrate;
providing a first strained layer disposed above the substrate, the first strained layer having an average surface roughness of no more than approximately 2 nm,
providing a gate stack disposed above the first strained layer; and
providing metal silicide regions,
wherein the first strained layer has an average surface roughness of less than approximately 0.77 nm.
49. The method of claim 48 , wherein the metal silicide regions comprise alloyed metal-SiGe.
50. The method of claim 48 , wherein the metal comprises Ni.
51. The method of claim 48 , further comprising providing source and drain contact areas.
52. The method of claim 51 , further comprising providing an additional SiGe or Ge layer in the source and drain contact areas prior to providing metal silicide regions.
53. The method of claim 48 , wherein the first strained layer is tensilely strained.
54. The method of claim 48 , wherein the first strained layer is compressively strained.