Methods of fabricating dual layer semiconductor devices

1. A method for fabricating a semiconductor-based device, the method comprising:

forming a channel layer by:

providing a compressively strained distal layer to support hole conduction for at least one p-channel component;

providing a proximal layer in contact with the distal layer and having a thickness less than approximately 4 nm that facilitates hole conduction by the distal layer, the channel layer comprising the distal and the proximal layers;

forming the at least one p-channel component; and

forming at least one n-channel component, the at least one p-channel component and the at least one n-channel component each having the channel layer in contact with a dielectric layer,

wherein the distal layer is in contact with an unstrained substrate layer.

2. The method of claim 1 , further comprising providing a substrate layer comprising silicon and germanium, and wherein the proximal layer comprises tensilely strained silicon, and the compressively strained distal layer comprises at least one of compressively strained silicon and germanium.

3. A method for fabricating a semiconductor-based device, the method comprising:

providing a distal material to support hole conduction for at least one p-channel component;

providing a proximal material in contact with the distal material and having a thickness less than approximately 4 nm that facilitates hole conduction by the distal material; and

forming the at least one p-channel component having a channel comprising a portion of the distal material and a portion of the proximal material,

wherein the channel of the at least one p-channel component is in contact with a dielectric layer, the distal material comprises compressively strained Si 1-y Ge y , and the strain in the distal material is induced by relaxed material in contact with the distal material.

4. The method of claim 3 , wherein the relaxed material comprises Si 1-x Ge x .

5. The method of claim 4 , wherein a difference between y and x is selected from a range of 0.2 to 0.4.

6. The method of claim 3 , wherein at least a portion of the channel is disposed above the relaxed material.

7. The method of claim 3 , wherein the channel comprises silicon.

8. The method of claim 3 , wherein the channel is disposed over the relaxed material.

9. The method of claim 3 , wherein forming the at least one p-channel component comprises forming a source and a drain proximate the channel, each of the source and the drain comprising compressively strained Si 1-y Ge y .

10. A method for fabricating a semiconductor-based device, the method comprising:

providing an n-channel component comprising a first strained silicon channel; and

providing a p-channel component comprising a second strained silicon channel proximate a dielectric layer;

wherein the second strained silicon channel is disposed proximate compressively strained Si 1-y Ge y , the n-channel component has a first drive current enhancement relative to an unstrained reference n-channel component, the p-channel component has a second drive current enhancement relative to an unstrained reference p-channel component, and the second drive current enhancement is larger than the first drive current enhancement.

11. The method of claim 10 , wherein forming the p-channel component comprises forming a source and a drain proximate the second strained silicon channel, each of the source and the drain comprising compressively strained Si 1-y Ge y , and forming the source and the drain comprises forming a germanosilicide contact in each of the source and the drain.

12. The method of claim 10 , wherein the first strained silicon channel is tensilely strained.

13. The method of claim 10 , further comprising:

forming a shallow trench isolation region proximate at least one of the n-channel component and the p-channel component.

14. The method of claim 13 , wherein the shallow trench isolation region is disposed proximate a material comprising compressively strained Si 1-y Ge y .

15. The method of claim 10 , wherein the n-channel component and the p-channel component define an inverter.

16. The method of claim 10 , wherein the first strained silicon channel and the second strained silicon channel both operate as surface channels during operation.

17. The method of claim 10 , wherein the n-channel component and the p-channel component are each provided over an insulating layer disposed within a substrate.

18. The method of claim 17 , wherein the insulating layer is disposed under and in direct contact with SiGe.