Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS
A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si 1-x Ge x layer on the Si substrate, and a strained surface layer on said relaxed Si 1-x Ge x layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed Si 1-x Ge x layer on the Si substrate, and a strained layer on the relaxed Si 1-x Ge x layer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.
1. A method of fabricating a CMOS inverter, the method comprising the steps of:
providing a heterostructure including a Si substrate, a Si 1-x Ge x layer on the Si substrate, and a strained layer on the Si 1-x Ge x layer, the heterostructure comprising an interface, located between the strained layer and the Si substrate, that exhibits a roughness less than 1 nm, whereby the strained layer exhibits a surface roughness less than 1 nm; and
integrating a pMOSFET and an nMOSFET in the heterostructure, wherein a channel of the pMOSFET and a channel of the nMOSFET are formed in the strained surface layer.
2. The method of claim 1 wherein the Si 1-x Ge x layer is relaxed.
3. The method of claim 1 wherein the heterostructure further comprises an underlying insulator layer.
4. The method of claim 1 wherein 0.1<x<0.5.
5. A method of fabricating an integrated circuit comprising:
providing a heterostructure having a Si substrate and a strained layer thereover, the strained layer exhibiting a surface roughness less than 1 nm; and
forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises a channel of at least one of the transistors, the transistors being interconnected in a CMOS circuit.
6. The method of claim 5 wherein the heterostructure further comprises an insulating layer below the strained layer.
7. The method of claim 5 wherein the heterostructure further comprises a SiGe graded buffer layer positioned between the relaxed Si 1-x Ge x layer and the Si substrate.
8. The method of claim 5 wherein the strained layer comprises Si.
9. The method of claim 5 wherein 0.1<x<0.5.
10. The method of claim 5 wherein the CMOS circuit comprises a logic gate.
11. The method of claim 10 wherein the logic gate is a NOR gate.
12. The method of claim 10 wherein the logic gate is an XOR gate.
13. The method of claim 10 wherein the logic gate is a NAND gate.
14. The method of claim 5 wherein the p-channel transistor serves as a pull-up transistor in the CMOS circuit and the n-channel transistor serves as a pull-down transistor in the CMOS circuit.
15. The method of claim 5 wherein the heterostructure further comprises a Si 1-x Ge x layer below the strained layer.
16. The method of claim 5 wherein an interface including an unexposed face of the strained layer exhibits a roughness less than 1 nm.