IP Library Granted Patent US 7,410,861
Granted Patent B2
US 7,410,861 · App. 10/966,959 · Granted Aug 12, 2008

Methods of forming dynamic random access memory trench capacitors

Assignee: AmberWave Systems Corporation
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Quick Facts
Patent No.
US 7,410,861
App. No.
10/966,959
Granted
Aug 12, 2008
Kind
B2
Abstract

DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.

Claims (72)

1. A method for forming a semiconductor structure, the method comprising:

forming a trench capacitor, including the steps of:

defining a trench in a portion of a semiconductor substrate, the trench having an interior surface and being disposed entirely within a region of the substrate substantially free of germanium,

introducing a first conductive material into the trench to define an outer plate,

forming an insulating layer on the outer plate, and

introducing a second conductive material into the trench to define an inner plate; and

forming a device on the substrate, the device comprising a strained channel.

2. The method of claim 1 , wherein the strained channel comprises strained silicon.

3. The method of claim 1 , wherein the strained channel is disposed proximate a material including SiGe.

4. The method of claim 1 , wherein the device comprises a transistor.

5. The method of claim 4 , wherein the transistor comprises an access transistor.

6. The method of claim 4 , wherein the transistor comprises an NMOS transistor.

7. The method of claim 4 , wherein the transistor comprises a PMOS transistor.

8. The method of claim 1 , further comprising:

providing a strain-inducing material over the substrate, the strain-inducing material comprising silicon,

wherein strain in the strained channel is induced by the strain-inducing material.

9. The method of claim 8 , wherein providing the strain-inducing material comprises deposition.

10. The method of claim 9 , wherein deposition comprises chemical vapor deposition.

11. The method of claim 8 , further comprising:

defining an isolation region proximate the strain-inducing material.

12. The method of claim 11 , wherein the isolation region comprises silicon dioxide.

13. The method of claim 1 , further comprising:

providing a strain-inducing material over the substrate, the strain-inducing material comprising germanium,

wherein strain in the strained channel is induced by the strain-inducing material.

14. The method of claim 13 , wherein providing the strain-inducing material comprises deposition.

15. The method of claim 14 , wherein deposition comprises chemical vapor deposition.

16. The method of claim 13 , wherein the strain-inducing material is at least partially relaxed.

17. The method of claim 13 , further comprising:

defining an isolation region proximate the strain-inducing material.

18. The method of claim 17 , wherein the isolation region comprises silicon dioxide.

19. The method of claim 1 , further comprising:

forming a second insulating layer, wherein the second insulating layer is disposed beneath the strained channel.

20. The method of claim 1 , wherein the insulating layer comprises silicon dioxide.

21. The method of claim 1 , wherein the insulating layer comprises nitrided silicon dioxide.

22. The method of claim 1 , wherein the insulating layer comprises an insulating material having a dielectric constant higher than a dielectric constant of silicon dioxide.

23. The method of claim 22 , wherein the insulating material comprises at least one of tantalum oxide and silicon nitride.

24. The method of claim 1 , wherein the first conductive material comprises polysilicon.

25. The method of claim 1 , wherein the second conductive material comprises polysilicon.

26. The method of claim 1 , wherein the outer plate comprises a conductive trench sidewall.

27. The method of claim 26 , wherein introducing the first conductive material into the trench to define an outer plate comprises defining the conductive trench sidewall by diffusing dopants into the trench sidewall.

28. The method of claim 27 , further comprising:

at least partially filling the trench with a sacrificial dopant source prior to diffusion; and

at least partially removing the sacrificial dopant source from the trench after diffusion.

29. The method of claim 28 , wherein the step of removing the dopant source comprises using a wet etch.

30. A method for forming a semiconductor structure, the method comprising:

forming a trench capacitor, including the steps of:

defining a trench in a portion of a semiconductor substrate, the trench having an interior surface and extending into a region of the substrate substantially free of germanium,

introducing a first conductive material into the trench to define an outer plate comprising a conductive trench sidewall defined by diffusing dopants into the trench sidewall,

forming an insulating layer on the outer plate, and

introducing a second conductive material into the trench to define an inner plate;

forming a device on the substrate, the device comprising a strained channel;

at least partially filling the trench with a sacrificial dopant source prior to diffusion; and

at least partially removing the sacrificial dopant source from the trench after diffusion,

wherein the dopant source comprises at least one of boron-silicate glass and phosphor-silicate glass.

31. The method of claim 26 , wherein introducing the first conductive material into the trench to define an outer plate comprises defining the conductive trench sidewall by implanting dopants into the trench sidewall.

32. The method of claim 26 , wherein defining the outer plate comprises forming the conductive trench sidewall by introducing dopants into the semiconductor substrate portion before defining the trench.

33. The method of claim 1 , wherein the strained channel is tensilely strained.

34. The method of claim 1 , wherein the strained channel is compressively strained.

35. The method of claim 1 , wherein the strained channel is proximate a material comprising strained SiGe.

36. The method of claim 1 , wherein forming the insulating layer comprises deposition.

37. The method of claim 36 , wherein deposition comprises chemical vapor deposition.

38. The method of claim 1 , wherein forming the insulating layer comprises growing the insulating layer.

39. A method for forming a semiconductor structure, the method comprising:

forming a trench capacitor, including the steps of:

defining a trench in a portion of a semiconductor substrate, the trench having an interior surface and being disposed entirely within a region of the substrate substantially free of germanium,

at least partially filling the trench with a sacrificial dopant source;

thereafter, introducing a first conductive material into the trench to define an outer plate comprising a conductive trench sidewall defined by diffusing dopants into the trench sidewall,

at least partially removing the sacrificial dopant source from the trench after diffusion,

forming an insulating layer on the outer plate, and

introducing a second conductive material into the trench to define an inner plate; and

forming a device on the substrate, the device comprising a strained channel,

wherein the dopant source comprises at least one of boron-silicate glass and phosphor-silicate glass.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2010
From: AMBERWAVE SYSTEMS CORPORATION
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 023848/0183 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2005
From: BULSARA, MAYANK; CURRIE, MATTHEW T.; LOCHTEFELD, ANTHONY J.
To: AMBERWAVE SYSTEMS CORPORATION
Reel/Frame 016680/0862 →
Continuity (3)
Continuation 1021800700 · Aug 13, 2002
Provisional Application 6031180100 · Aug 13, 2001
Related Publication 20050067647A1 · Mar 31, 2005