Methods for preserving strained semiconductor substrate layers during CMOS processing
Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad oxide, are formed by deposition onto, rather than reaction with and consumption of the surface layer. Alternatively, oxide deposition is preceded by a thermal oxidation step of short duration, e.g., rapid thermal oxidation. Here, the short thermal oxidation consumes little surface Si, and the Si/oxide interface is of high quality. The oxide may then be thickened to a desired final thickness by deposition. Furthermore, the thin thermal oxide may act as a barrier layer to prevent contamination associated with subsequent oxide deposition.
1. A method for forming a structure, the method comprising:
forming a strained semiconductor layer over a substrate, the strained semiconductor layer comprising at least one III-V compound;
growing an oxide layer over at least a portion of a top surface of the strained semiconductor layer;
depositing a pad oxide layer over the oxide layer; and
forming a masking layer over the pad oxide layer,
wherein the pad oxide layer substantially inhibits formation of stress-induced defects in the strained semiconductor layer.
2. The method of claim 1 wherein the masking layer comprises silicon nitride.
3. The method of claim 1 wherein the oxide layer is grown by a rapid thermal oxidation.
4. The method of claim 1 wherein a thickness of the oxide layer is selected from a range of about 5 Å to about 30 Å.
5. The method of claim 1 wherein the substrate comprises at least one of silicon, germanium, or a III-V compound.
6. The method of claim 1 wherein the strained semiconductor layer is tensilely strained.
7. The method of claim 1 wherein the strained semiconductor layer is compressively strained.
8. The method of claim 1 wherein a thickness of the strained semiconductor layer is selected from a range of about 50 Å to about 1000 Å.
9. The method of claim 8 wherein a thickness of the strained semiconductor layer is less than or equal to about 300 Å.
10. The method of claim 8 wherein the thickness of the strained semiconductor layer is substantially unchanged following the deposition of the pad oxide layer.
11. The method of claim 1 wherein the substrate comprises an insulating layer disposed underneath the strained semiconductor layer.
12. The method of claim 1 wherein the substrate comprises a relaxed semiconductor layer disposed underneath the strained semiconductor layer.
13. The method of claim 12 wherein the substrate comprises a compositionally graded layer disposed underneath the relaxed semiconductor layer.
14. The method of claim 12 wherein the relaxed semiconductor layer comprises a III-V compound.
15. The method of claim 14 wherein the relaxed semiconductor layer comprises at least one of indium gallium arsenide and aluminum gallium arsenide.
16. The method of claim 1 wherein the step of depositing the pad oxide layer comprises chemical vapor deposition.
17. The method of claim 1 wherein the pad oxide layer is selected from the group consisting of: silicon dioxide, silicon oxynitride, silicon germanium oxide, and germanium oxide.
18. A method for forming a structure, the method comprising:
forming a semiconductor layer over a substrate, the semiconductor layer comprising at least one III-V compound;
depositing a pad oxide layer over at least a portion of a top surface of the semiconductor layer;
forming a masking layer over the pad oxide layer, wherein the pad oxide layer substantially inhibits formation of stress-induced defects in the semiconductor layer; and
processing the substrate to form a CMOS device thereover, the CMOS device having a strained channel disposed in the semiconductor layer,
wherein processing the substrate comprises forming a shallow trench isolation region proximate the CMOS device.
19. The method of claim 18 , further comprising, prior to depositing the pad oxide layer, growing an oxide layer over the portion of the top surface of the semiconductor layer.
20. A method for forming a structure, the method comprising:
forming a semiconductor layer over a substrate;
inducing strain in the semiconductor layer to enhance carrier mobility in a MOSFET;
depositing a pad oxide layer over at least a portion of a top surface of the first semiconductor layer;
forming a masking layer over the pad oxide layer; and
forming a shallow trench isolation region by etching a portion of the semiconductor layer,
wherein the pad oxide layer substantially inhibits formation of stress-induced defects in the semiconductor layer during formation of the shallow trench isolation region.
21. The method of claim 20 , further comprising:
prior to depositing the pad oxide layer, growing an oxide layer over the portion of the top surface of the strained semiconductor layer,
wherein the strained semiconductor layer comprises at least one III-V compound.
22. A method for forming a structure, the method comprising:
forming a strained semiconductor layer over a substrate, the strained semiconductor layer comprising at least one III-V compound;
depositing a pad oxide layer over at least a portion of a top surface of the strained semiconductor layer; and
forming a masking layer over the pad oxide layer,
wherein the pad oxide layer substantially inhibits formation of stress-induced defects in the strained semiconductor layer and the pad oxide layer comprises at least one of silicon oxynitride, silicon germanium oxide, or germanium oxide.