Granted Patent B1

US 7,035,908 · App. 09/915,833 · Granted Apr 25, 2006

Abstract

Claims (35)

1. An apparatus comprising:

a system bus;

a shared memory (i) coupled to said system bus and (ii) configured to store data; and

a multiprocessor logic circuit comprising (i) a plurality of processors and (ii) a message circuit comprising a message pipe-line FIFO, wherein (a) said message circuit is directly connected to said system bus and configured to pass messages between said plurality of processors, (b) each of said plurality of processors is directly connected to said system bus and configured to access said shared memory and said message circuit through said system bus and (c) said message circuit is further configured to add commands written to a first address with normal priority levels and add commands written to a second address with urgent priority levels.

2. The apparatus according to claim 1 , wherein said message circuit comprises a dedicated messaging circuit.

3. The apparatus according to claim 1 , wherein said message circuit is further configured to provide bi-directional orderly command passing.

4. The apparatus according to claim 1 , wherein said message circuit is further configured to generate one or more control signals configured to control an operation of said plurality of processors.

5. The apparatus according to claim 4 , wherein said control signals comprise signals selected from the group consisting of (i) pipe-line overflow signals, (ii) pipe-line available signals, and (iii) command pending signals.

6. The apparatus according to claim 1 , wherein said multiprocessor logic circuit further comprises:

an address decoder configured to decode a system address and control said message circuit.

7. The apparatus according to claim 1 , wherein said apparatus provides a multiprocessor communication and shared memory architecture.

8. The apparatus according to claim 1 , wherein:

said multiprocessor logic block further comprises an address decoder configured to generate one or more first control signals configured to control said message circuit; and

said message circuit is configured to generate one or more second control signals configured to control said processors.

9. A method for multiprocessor communication with a shared memory, comprising the steps of:

(A) storing data with said shared memory;

(B) processing data with a plurality of processors;

(C) passing messages between said processors with a message circuit, wherein (i) said message circuit comprises a message pipe-line FIFO, (ii) each of said plurality of processors and said message circuit are directly connected to a system bus, and (iii) each of said plurality of processors is configured to access said shared memory and said message circuit through said system bus; and

(D) adding commands (i) written to a first address with normal priority levels and (ii) written to a second address with urgent priority levels.

10. The method according to claim 9 , wherein step (C) further comprises:

providing bi-directional orderly command passing.

11. The method according to claim 10 , wherein step (C) further comprises:

generating one or more control signals, said control signals configured to control an operation of said processors.

12. The method according to claim 11 , wherein said control signals comprise signals selected from the group consisting of: (i) pipe-line overflow signals, (ii) pipe-line available signals, and (iii) command pending signals.

13. The method according to claim 9 , wherein:

said adding commands with normal priority levels further comprises adding commands to an end of a message queue; and

said adding commands with urgent priority levels further comprises adding commands near to a front of said message queue.

14. The method according to claim 9 , wherein step (C) further comprises:

decoding a system address.

15. The method according to claim 14 , wherein step (C) further comprises:

controlling said messages in response to said decoded system address.

16. An apparatus comprising:

a system bus;

a shared memory (i) coupled to said system bus and (ii) configured to store data; and

a multiprocessor logic circuit comprising (i) a plurality of processors and (ii) a message circuit comprising a message pipe-line FIFO, wherein (a) said message circuit is directly connected to said system bus and configured to pass messages between said plurality of processors, (b) each of said plurality of processors is directly connected to said system bus and configured to access said shared memory and said message circuit through said system bus, (c) said message circuit is further configured to generate one or more control signals configured to control an operation of said plurality of processors, and (d) said control signals comprise signals selected from the group consisting of (i) pipe-line overflow signals, (ii) pipe-line available signals, and (iii) command pending signals.

Assignments (8)